Shriram Kulkarni
2055 Commerce Blvd, Apt 121
Ann Arbor, MI 48103
+1 (734) 668-0627
shriram@umich.edu
OBJECTIVE Seeking a position that will allow me to apply my skills to VLSI circuit design challenges in next-generation computing and communication systems.
EDUCATION
Ph.D.
1999 		The University of Michigan, Ann Arbor
Electrical Engineering. Dissertation: Quantum MOS Circuits and Systems
M.S.
1995 		The University of Michigan, Ann Arbor
Electrical Engineering (VLSI major). GPA 7.9 (A=8.0).
B.E.
1991 		Karnataka Regional Engineering College, Surathkal, India
Electrical Engineering. GPA: 3.8 (A=4.0).
EXPERIENCE
Research Fellow
2000-present 		The University of Michigan, Ann Arbor
  • Developed BISRAMGEN, an advanced memory compiler with programmable self-test and repair, defect coverage analysis, and SPICE-based design cornering.
  • Conducted research in circuit and system applications of resonant tunneling diodes.
  • Wrote proposals for future research projects in the area of quantum-effect circuits, fault tolerance and VLSI CAD.
  • Reviewed papers for IEEE Transactions on VLSI and for Electronics Letters.
    • Research Assistant
    1993-99     		The University of Michigan, Ann Arbor
    Advisor: Prof. Pinaki Mazumder.
  • Invented low power-delay bistable logic topologies using resonant tunneling diodes.
  • Theoretically analyzed quantum-effect circuit noise, speed and power performance.
  • Demonstrated quantum-effect circuit based system architecture prototypes.
  • Developed zero-delay overhead SRAM self-repair scheme for a memory compiler.
  • Wrote research grants funded by NSF, DARPA, and Army Research Office.
    • Teaching Assistant
    1992-94, 97     		The University of Michigan, Ann Arbor
    Professors: Dr. Ronald J. Lomax and Dr. Pinaki Mazumder.
  • Developed course material, designed lab experiments, moderated class discussions, lectured classes, graded assignments and assisted a total of about 450 students in "VLSI Design I", EECS427 and "Introduction to Digital Logic Design," EECS270.
    • PATENTS,
    PUBLICATIONS,
    AND PAPERS
  • S. Kulkarni, P. Mazumder, and G. I. Haddad, "Digital Logic Gate Design Using NDR Diodes and FETs," U.S. Patent No. 5,903,170, May 1999.
  • S. Kulkarni, M. Bhattacharya, and P. Mazumder, "Edge-Triggered Flip-Flop Circuits Using NDR Diodes and FETs," U.S. Patent pending, May 2000.
  • P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun, and G. I. Haddad, "Digital Circuit Applications of Resonant-Tunneling Devices," Proceedings of the IEEE, vol. 86, no. 4, April 1998, pp. 664-686.
  • K. Chakraborty, S. Kulkarni, M. Bhattacharya, P. Mazumder, and A. Gupta, "A Physical Design Tool for Built-In Self-Repairable RAMs," IEEE Transactions on VLSI, accepted for publication, July 2000.
  • A. F. Gonzalez, M. Bhattacharya, S. Kulkarni, and P. Mazumder, "CMOS Implementation of a Multiple-Valued Logic Signed-Digit Full Adder Based on Negative-Differential-Resistance Devices," IEEE Journal of Solid State Circuits, accepted for publication, September 2000.
  • A. F. Gonzalez, M. Bhattacharya, S. Kulkarni, and P. Mazumder, "Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative-Differential-Resistance Devices," in Proceedings of the International Symposium on Multiple-Valued Logic, pp. 323-328, 2000.
  • M. Bhattacharya, S. Kulkarni, A. F. Gonzalez, and P. Mazumder, "A Prototyping Technique for Large-Scale RTD-CMOS Circuits," in Proceedings of the International Symposium on Circuits and Systems, pp. I-635-638, 2000.
  • S. Kulkarni and P. Mazumder, "Circuit Applications of Quantum MOS Logic," in Proceedings of the European Conference on Circuit Theory and Design, pp. 667-670, 1999.
  • K. Chakraborty, A. Gupta, M. Bhattacharya, S. Kulkarni, and P. Mazumder, "A Physical Design Tool for Built-in Self-repairable Static RAMs," in Proceedings of Design and Test Automation in Europe, 1999.
  • N. Deb, J. Xiong, M. Bhattacharya, S. Kulkarni and P. Mazumder, "Analysis of Switching Speed and Power Dissipation of RTD-CMOS Bistable Logic Gates," Proceedings of Silicon Nanoelectronics, June 1998.
  • S. Kulkarni and P. Mazumder, "A Full Adder Circuit Using RTDs and MOSFETs," Proceedings of the Government Microelectronics Applications Conference, Arlington, VA, March 1998.
  • P. Mazumder, S. Kulkarni, M. Bhattacharya, and A. Gonzalez, "Design and Simulation of Resonant Tunneling Diode Circuits," Proceedings of the 11th IEEE International VLSI Conference, Chennai, India, January 1998.
  • S. Kulkarni, P. Mazumder and G. I. Haddad, "A High-speed 32-bit Parallel Correlator for Spread Spectrum Communication," Proceedings of the 9th International Conference on VLSI Design, Bangalore, India, January 1996.
  • S. Kulkarni, P. Mazumder and G. I. Haddad, "A 32-bit Ultrafast Parallel Correlator using Resonant Tunneling Devices," Proceedings of the International Conference on Micro-nanotechnology for Space Applications, Houston, TX, October 1995.
    • SKILLS
  • Microprocessor and communication system IC design using Cadence Verilog, Mentor Graphics, Avanti, Cascade, UC-Berkeley and U-Michigan CAD tools.
  • Analog and digital IC fabrication, and testing using HP high-speed test equipment.
  • 100,000 lines of code written in C, Perl, Tcl/Tk for memory compiler BISRAMGEN.
  • Assembly programming on Motorola and TI DSPs to implement CDMA protocols.
    • AWARDS
    Sustained Excellence
    1998     		Defense Advanced Research Projects Agency, ULTRA Electronics Program
    Awarded to the Quantum MOS team, of which I am a member, comprising researchers from several institutions working on DARPA-funded quantum electronics research programs.
    Outstanding TA
    1994     		Electrical Engineering and Computer Science Department, The University of Michigan, Ann Arbor
    Annual award presented to the outstanding teaching assistant in the department.