A number of your grades are incorrect as posted.
Our new baby came just after the final, and I was in a hurry to get grades in on time. Please check this pdf file
for your actual grade. I will get grade change forms in as soon as possible,
though it might take a couple of weeks for the correct grades to work their
way through the system. Sorry for the confusion.
Your graded finals are available outside my office. The mean was 129 of 200.
We will open the lab as our schedules allow from today (Sunday) through the end of the week.
Because the TAs have finals and projects also, and Prof. Reinhardt and
his wife are expecting an overdue baby, we cannot commit to a specific
schedule. We will try to keep the lab unlocked while we are in the building; if you would like to check whether the lab is open, call the lab (936-0392)
and see if anyone answers.
Final exam news:
The final exam will be Fri. 12/18 1:30-3:30 PM.
Last names A-Q go to the regular lecture room; last names R-Z
go to 2233 GGB.
Unlike the midterms, the final will not be open
book/notes.
Two review sessions will be held: Wed 12/16 and Thu 12/17
starting at 7 PM in 1504 GGB.
Lab 7 news: According to Erik, ``the current lab 7 bugs
are fixed,'' so students from Monday and Tuesday labs who were
unable to get Lab 7 working can come back in and should be
able to finish now. Apparently the Xilinx default behavior is
not what we thought, so a number of control signals must be
tied to suitable values for things to work reliably.
Students with last names R-Z should go to 1005 EECS for the exam
on Tue 11/10.
Lab 5 is a two-week lab: prelabs will be due 11/4-11/10, and the
final lab reports will be due 11/18-11/24. However, the TAs will be
doing a tutorial on the Xilinx FPGA design software during the lab section
meetings for the week 11/11-11/17, so you will not have the full three
hours to work on Lab 5 that week.
If you've been having trouble loading your interrupt vector code into the simulator, read this.
Lab 5 is ready. You will have two weeks to do Lab 5, although the second week of lab section meetings will be used for the TAs to introduce the Xilinx FPGA software.
Lab 3 is now a two-week lab. Your prelabs are still due this
week (Oct. 7-13) but you will have two lab sections to work on the
lab, and the final lab report will be due the week of Oct. 21-27.
If you turn your report in after one week (in your lab section
Oct. 14-20) you will get a 10% extra-credit bonus on the lab.
Since some people have had trouble with the news server,
I copied the postings referred to previously to this web
site:
Check the newsgroup
(umich.eecs.class.373) for a few important announcements
on subtract opcodes, bogus assembler warnings that you
will see in Lab 2, and getting a copy of the SingleStep
simulator for use at home. (Note: if you can't find these
announcements, make sure your news reader is talking to
"news.eecs.umich.edu". These postings will
eventually propagate to other news hosts, but slowly...)