EECS 470 Course Information

Winter 1998

Course Objectives

EECS 470 is an introductory graduate-level course in computer architecture. This course is intended to do two things:

1. to give you a solid, detailed understanding of how computers are designed and implemented, including the central processor and memory and I/O interfaces, and
2. to make you aware of the numerous tradeoffs in design and implementation, their interaction, their realization in both historical and state-of-the-art systems, and trends that will affect them in future systems.

We will cover instruction set architectures, pipelining (including basic pipelining, multiple-instruction-per-cycle machines, out-of-order instruction execution, and vector processing), memory systems (including caches and virtual memory), I/O interfaces, operating system issues, and (if time permits) basic multiprocessor systems.

A central part of EECS 470 is the detailed design of a substantial, realistic processor using the Verilog hardware design language. You will use modern commercial CAD tools, provided by Cadence Design Systems, Inc., to develop and test your design. This project represents a significant investment of time on your part, and is a significant portion of your grade in this class. However, in computer architecture it is particularly true that "the devil is in the details", and you will gain important experience and knowledge by coming face to face with that devil.

EECS 370 is a prerequisite for this course. I will assume that you have a solid understanding of the material covered in that course: assembly language, machine language, ALU design, and the basic ideas of pipelining, caches, and virtual memory. EECS 470 expands on this material greatly in both depth and breadth. If you did not take EECS 370 here, you may need to spend extra time reviewing this material. I have placed the EECS 370 textbook (Patterson & Hennessy's Computer Organization & Design: The Hardware/Software Interface) on reserve at the library for that purpose.

Meeting Times

Lecture: 3:30-5:00 MW 1003 EECS
Discussion: 3:30-4:30 F 1003 EECS (mandatory)

Instructor

Professor Steven K. Reinhardt (stever@eecs.umich.edu), 2223 EECS, 647-7959
Office hours: Tuesday 4-5, Thursday 11-12, or by appointment (send email).

Textbook etc.

Required text:

Computer Architecture: A Quantitative Approach (Second Edition), John L. Hennessy & David A. Patterson (Morgan Kaufmann, 1996). Make sure you have the second edition and not the first (it's changed significantly).

Additional texts: (on reserve at the library)

Computer Architecture: Pipelined and Parallel Processor Design, Michael J. Flynn (Jones & Bartlett, 1995).
Computer Organization (Fourth Edition), V. Carl Hamacher, Zvonko G. Vranesic, and Safwat G. Zaky (McGraw Hill, 1996).
Computer Architecture and Organization (Second Edition), John P. Hayes, (McGraw Hill, 1988).
Computer Organization & Design: The Hardware/Software Interface (Second Edition), David A. Patterson & John L. Hennessy (Morgan Kaufmann, 1998). The first edition is on reserve until the library gets a copy of the second edition, which should be soon.

Additional papers that supplement the text will be handed out in class as needed.

Teaching Assistant

Erik Hallnor (ehallnor@engin.umich.edu). Office hours and location TBD.

On-Line Resources

• The course web page (http://www.eecs.umich.edu/~stever/470) has pointers to a lot of necessary information, including this handout and the schedule for lecture topics and readings.
• The course news group umich.class.eecs.470 will be used to answer both content-related and procedural questions. Please post your questions in the newsgroup; another student may be able to answer your question more quickly than the professor or TA. If you email a question to the professor or the TA, your question and our response will be posted to the newsgroup so that everyone can benefit (unless your question is obviously confidential in nature).
• Announcements will be posted to the web page and to the news group. You are responsible for checking both of these places regularly.

Course Policies

• Attendance at the discussion section is mandatory. The TA will hand out homework assignments and present vital information on the CAD tools you will be using for your project. Do not register for this course unless you can attend the discussion section.
• This course is a lot of work. You will spend many long nights debugging your processor at the end of the term. If you are registered for other classes that may interfere with your ability to dedicate a lot of time to this course, especially in the last few weeks, you should reconsider your schedule. If you have any doubts, talk with someone (such as the TA) who has taken the course from Prof. Patt or Prof. Davidson.
• You are encouraged to interact with other students to discuss course material, form study groups for the exams, help each other learn Verilog and the CAD tools, and provide each other with debugging assistance, encouragement, and moral support. However, the honor code is still in force: all individual assignments (i.e., homeworks and exams) are to be performed on your own, and all group assignments (i.e., the final project) are to be performed only by members of the group.  Violation of this policy is grounds for initiating an action that would be filed with the Dean's office and would come before the College of Engineering's Honor Council. If you have any doubts about whether your level of collaboration is permissible, contact the professor or the TA first.

Grading

Item	Weight
Homeworks	10%
Project	40%
Midterm	15%
Final	35%

Schedule

• The midterm exam will be given in class on Wednesday, Feb. 25 (Ash Wednesday). The final exam will be Thursday, April 23, 1:30-3:30. Let me know within the first two weeks if you have any conflicts with these times or if you need any special accomodations. After the first two weeks, exams will be rescheduled only in the case of extreme, documented emergencies.
• Project dates (subject to change): proposals due 3/11 in class, initial design reviews 3/12-3/14, final design reviews 4/16-4/18, final report due 4/20 in class.
• See the web page for lecture topics and reading assignments.