Homework 2

EECS 470, Winter 1998

Reinhardt

Due January 23,1998

 

16-bit ALU Simulation
  1. First extend the ALU you designed in HW1 as follows: Connect the output of the ALU to a 16-bit register called ALUout made of edge-triggered D flip flops. Connect 16-bit 2-1 MUXes to each input of the ALU and call them muxa and muxb. Connect the Q outputs of ALUout to inputs of both muxa and muxb.
  2. Translate this circuit into Verilog. All parts should be constructed structurally using only NAND or NOR gates contained in lib1. You can use the library part dff$ to construct the 16-bit register. Use the typical delays given for your library parts.
  3. Create a behavioral clock in the TOP module. Set the cycle time for 100ns. The D flip flops are clocked with this signal. Apply the appropriate input patterns specified in the TOP module using the initial statement. You may assume that input changes (including the select inputs) are synchronized with the positive edge of the clock.
  4. Using the typical delays, calculate the worst case delay, which is the minimum cycle time. Recall that the data must be setup for a certain time before being latched into the flip-flops.
  5. Using Verilog, verify correctness of both your ALU design and your timing calculations by applying test cases and verifying the results. Use signalscan to generate timing diagrams, and print out hardcopies to turn in.
  6. Gradually reduce the cycle time. Find the minimum possible cycle time that will not cause any timing problems in the circuit. Recall that the sum of the delays along the feedback path, plus the setup time of the d flip flop should not be greater than the cycle time. Is your calculation consistent with that observed in the calculations.
  7. Prepare a short report on the work done in steps 3-6, including plots of the schematics and the simulation results of your selected test patterns.