Homework 3

EECS 470, Winter 1998

Reinhardt

Due February 6, 1998

 

 

PowerPC Architecture

  1. Describe using register transfer notation the functionality of the following subset of the PowerPC architecture:

    Instructions: add, add., addo, addo., addc, addc., addco, addco., adde, adde., addeo, addeo., addi, addic, lwz, lwzx, stw, stwx, b, bl

    Data types: Word (32-bit)

  2. Design the datapath and an accompanying state diagram to implement the subset of the PowerPC described in part 1. Your state diagram should show all the relevant states. The datapath need show only the information paths, not control signals.

  3. You can use all the library parts for this assignment including the 4-bit ALU slice. Please hand in all circuit diagrams for your design. You may create dummy modules in Verilog to generate the control signals. For example:

    Module ALU_control (opcode, alu_control_signals);

    Input [N:0] opcode;

    Output [M:0] alu_control_signals;

    <…>

    endmodule

    For this assignment no simulation is necessary, but it should compile correctly. Please put a copy of your finished code in a directory hw3 in your class directory.

  4. For the design in part 2, select 5 instructions and calculate the number of cycles needed to execute each instruction. Start counting cycles at the beginning of its fetch cycle and end with its completion. For purposes of this assignment only assume a 10 nsec cycletime, single cycle cache access, 100 nsec memory access, D-cache hit ratio of 0.80, I-cache hit ratio of 0.95, and no page faults. Please show your calculations.