Homework 4

EECS 470, Winter 1998

Reinhardt

Due February 20, 1998

 

 

PowerPC Architecture
  1. Expand your datapath to include the following instructions:

    cmpi, cmp, cmpli, cmpl, andi., andis., xori, xor, xor., rlwinm, rlwinm., srw, srw., lwzu, lwzux, stwu, stwux, bc, bcl, bclr, bclrl, crand, mcrxr

  2. Specify the mechanism for generating the control signals that control the datapath. If you are planning to use hardwired control, this means specifying the finite state machine. If you are planning to use microprogrammed control (like the LC-2), this means specifying the microinstruction, its fields, the micro-orders that make up each field, and the microsequencer for obtaining the address of the nex microinstruction. If you want to pipeline your design (required for the project), then it is important to provide not only control of each instruction through the pipeline, but also provide sufficient interlocks to ensure safe execution of the instruction sequence (i.e. scoreboarding).

    Hand in hard copies of the schematics of the control structure you create.

  3. Specify all the control logic required to completely emulate one PowerPC instruction from fetching the instruction to storing the result. Use Verilog to simulate and verify that your design works for that one instruction. Use signalscan to monitor important data and signals in the CPU. Hand in annotated hard copies of your signalscan graphs. Use several pages if needed, and make sure that the values of all signals are readable on the printouts.

  4. Hand in a block diagram of your datapath with explanations to clarify what the signals on the signalscan graphs refer to.