This assignment should be done in conjunction with your partners. This is the design you will work on together until the end of the term.

1. Due 2/23/98 -- Turn in a sheet with your names and unique names during class.

Parts 2-6 are due at the time of your design review.

2. Implement all of the internal functionality described in the project specifications. Turn in schematics of all the hardware used to implement this functionality.
3. Design an external bus interface. It should process memory accesses and external interrupts. Your design should include a description of bus signals and of bus protocols. Hand in a description of your bus interface.
4. Construct a hierarchical block diagrams of your machine. These diagrams should proceed for the very high level, to the higher functional blocks (e.g. Data Path, Control, Cache Memory, Main Memory, etc.), to the lower functional block (e.g. ALU, Shifter, Regfile, Intermediate registers, etc.). The diagrams should show interconnections between the functional blocks. Be as detailed as necessary. Hand in block diagrams.
5. Construct a detailed schedule for the design of your machine. Estimate how much time you expect to spend designing, simulating and debugging each component on the Verilog System. Allow yourself as much debugging time as possible, since the debugging process can be extremely time consuming. It will be advantageous to leave some time for critical path analysis and redesign.
6. Coordinate with your partners and sign up for a time for a preliminary design review. These will take place the second week after break. They will nominally take 45 minutes. A sign up sheet will be posted before the due date of the assignment. All members of your group must attend the preliminary design review. If you cannot find a time when all the members can attend please see us.