• Must have at least a 3-stage pipeline.
• Must eliminate at least one data hazard by forwarding.
• Graded on many factors including benchmark performance and cycle time. A cycle time greater than 20ns will be severely downgraded.
• Registers:
  • 32 General Purpose Registers
  • CR, XER, LR, CTR
  • Configuration Registers -- MSR (only pertinent bits)
  • Memory Management Registers -- 16 Segment Registers
  • Exception Handling Registers -- DAR, DSISR, SRR0, SRR1
• Instructions:
  • All integer arithmetic instructions, except multiplies and divides
  • All integer compare instructions
  • All integer logical instructions, except 64-bit only instructions
  • All integer rotate instructions, except 64-bit only instructions
  • All integer shift instructions, except 64-bit only instructions
  • All integer load instructions, except 64-bit only instructions
  • All integer store instructions, except 64-bit only instructions
  • All branch instructions
  • All condition register logical instructions
  • Move to/from condition register instructions
  • Move to/from special-purpose register instructions
  • System Call (sc) and Return from Interrupt (rfi)
• Exceptions:
  • DSI
  • ISI
  • External Interrupt
  • System Call
• Memory:
  • Segmented Access, no Direct-Store segments
  • Real Addressing Mode
  • TLB consisting of a valid bit, a present bit, a non-cacheable bit, the virtual page number, the physical frame number, a user/supervisor (U/S) bit and a read/write bit (R/W). If the U/S bit is set to one, then the page can only be accessed in supervisor mode. If the R/W is zero then it is read only.
  • 1K Instruction Cache
  • 1K Data Cache
• External Bus:
  • 64-bit bus
  • 8k of Memory (location specified later, for now assume 1K blocks)

These specifications are subject to change, so please check back regularly. Also, any extensions to these specification will be considered for extra credit.