| Week | Lecture 1 | Lecture 2 | Discussion |
| Jan 5 | (none) | Course intro, cost, performance [Ch. 1] | Intro to Verilog |
| Jan 12 | ISAs [Ch. 2] | ISAs cont'd [Appendices C & D] | Review of non-pipelined implementation; homework 1 due |
| Jan 19 | NO CLASS (MLK Day) | ISAs cont'd | Verilog tools cont'd, PowerPC ISA |
| Jan 26 | Bhandarkar & Clark, Smith & Weiss; Basic Pipelining [Ch 3] |
Basic Pipelining cont'd; homeworks 2 & 2b due |
Pipeline implementation example |
| Feb 2 | Basic Pipelining cont'd | Caches [5.1-5.6] | homework 3 due; discuss homework 4 |
| Feb 9 | Caches cont'd | Caches cont'd | Term project discussion |
| Feb 16 | Virtual Memory [5.7-5.13] | Virtual Memory cont'd | project discussion cont'd; homework 4 due |
| Feb 23 | Review | Midterm | No meeting |
| Mar 2 | NO CLASS (Spring Break) | NO CLASS (Spring Break) | NO CLASS (Spring Break) |
| Mar 9 | Go over midterm | Go over midterm (cont'd) | Finish virtual memory |
| Mar 16 | Initial design reviews (no class) | Buses & I/O [Ch 6] | Project discussion (as needed) |
| Mar 23 | Advanced Pipelining [Ch 4] | Advanced Pipelining cont'd | Project discussion (as needed) |
| Mar 30 | Advanced Pipelining cont'd | Advanced Pipelining cont'd | Project discussion (as needed) |
| Apr 6 | Advanced Pipelining cont'd | Vector processors [App. B] | Multiprocessors [Ch 8] |
| Apr 13 | Multiprocessors cont'd | Case Studies | final design reviews |
| Apr 20 | Case Studies cont'd; final project report due in class | NO CLASS (Study Day) | NO CLASS (Exams) |