BulletProof: Defect-Tolerant Architectures

Representative publication: Kypros Constantinides, Smitha Shyam, Sujay Phadke, Valeria Bertacco and Todd Austin, “Ultra Low-Cost Defect Protection for Microprocessor Pipelines", International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, October 2006.

Project Synopsis: The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. PI Austin and his research team at University of Michigan are addressing these challenges through the StoneShield project, which is developing ultra low-cost mechanisms to protect a microprocessor pipeline and on-chip memory system from silicon defects. While traditional defect tolerance techniques require at least 100% overhead due to duplication of critical resources, the BulletProof project is exploiting the use of on-line testing-based approaches, which provide the same level of protection with overheads of less than 5%. The BulletProof team is developing novel ultra low-cost mechanisms to protect a microprocessor pipeline and on-chip memory system from silicon defects. To achieve this goal they combine area-frugal on-line testing techniques and system-level check-pointing to provide the same guarantees of reliability of traditional solutions, but at much lower cost. Their approach utilizes a microarchitectural check-pointing mechanism to create coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity of the underlying hardware. In case a failure is detected, they rely on the natural redundancy of instruction-level parallel (ILP) processors to repair the system such that it can still operate in a degraded performance mode.
 

Razor: Low-Power Processor Designs based on Timing Speculation

            

Representative publication: Todd Austin, David Blaauw, Trevor Mudge, and Krisztián Flautner, “Making Typical Silicon Matter with Razor”, IEEE Computer, March 2004.

Project Synopsis: The Razor team have been engaged in the development of Razor Logic and computer system simulation infrastructure used to evaluate Razor Logic. Razor is an error-tolerant dynamic voltage scaling technology capable of shaving away voltage margins, resulting in more energy efficient designs with little performance impact. The key observation underlying the design of Razor is that the worst-case conditions that drive traditional design are improbable conditions. Thus, by building error detection and correction mechanisms into the Razor design, it becomes possible to tune voltage to typical energy requirements, rather than worst case. The resulting design has significantly lower energy requirements, even in the presence of added energy processing requirements due to occasional error recoveries. The Razor design utilizes an in-situ timing error detection and correction mechanism implemented within the Razor flip-flop. Razor flip-flops double-sample pipeline stage values, once with an aggressive fast clock and again with a delayed clock that guarantees a reliable second sample. A metastability-tolerant error detection circuit is employed to check the validity of all values latched on the fast Razor clock. In the event of a timing error, a modified pipeline flush mechanism restores the correct stage value into the pipeline, flushes earlier instructions, and restarts the next instruction after the errant computation.
 

Subliminal Systems: Ultra Low-Power Processing with Subthreshold Circuits

     

Representative publication: Leyla Nazhandali, Bo Zhai, Ryan Helfand, Michael Minuth, Javin Olson, Sanjay Pant, Anna Reeves, Todd Austin, and David Blaauw, “Energy Optimization of Subthreshold-Voltage Sensor Processors,” in the 32nd Annual International Symposium on Computer Architecture (ISCA-2005), June 2005.

Project Synopsis: Sensor network processors and their applications are a growing area of focus in computer system research and design. Inherent to this design space is a reduced processing performance requirement and extremely high energy constraints, such that sensor network processors must execute low-performance tasks for long durations on small energy supplies. In the Subliminal Systems project, we are demonstrating that subthreshold-voltage circuit design (400 mV and below) lends itself well to the performance and energy demands of sensor network processors. Moreover, we have shown that the landscape for microarchitectural energy optimization dramatically changes in the subthreshold domain. The dominance of leakage power in the subthreshold regime demands architectures that i) reduce overall area, ii) increase the utility of transistors, while iii) maintaining acceptable CPI efficiency. Our best sensor platform, implemented in 130nm CMOS and operating at 235 mV, only consumes 1.38 pJ/instruction, nearly an order of magnitude less energy than previously published sensor network processor results. This design, accompanied by bulk-silicon solar cells for energy scavenging, has been manufactured by IBM.
 

Past Projects

• DIVA - Dynamic Instruction Verification Architectures
• Cyclone - Decentralized Dynamic Scheduler Architectures
• CryptoManiac - Application-Specific Processor Design
• The SimpleScalar Tool Set - Architectural Performance Analysis Tools