1 Background

For background, I work in an Advanced Development/Research group in the Digital Semiconductor division of Digital Equipment Corporation. Our group's work is focussed on architecture and compiler-related topics for future processors. The objective of the computer architecture work is usually to research promising ideas for processors that will be shipped in 5 or more years. The work can precede actual design by 2 to 3 years, and can continue in parallel with development, delivering ever smaller refinements until the design has frozen. My recent research interests include simultaneous multithreaded processors, prediction mechanisms, cache organization and cache hierarchies, VLIW and issues related to speculative execution.

2 Philosophical Context

I believe that computer architecture research should and does span a spectrum of activities from the incremental to the revolutionary. I further believe that it is important for the computer architecture community to pursue projects throughout this spectrum.

Incremental research activities involve refinement and characterization of well known concepts and structures, e.g., caches or pipeline organization. This work is characterized by the fact that it is invariably limited by the current (or near future) technology constraints and involves improving solutions to well defined problems, like branch prediction, or exploring the impact of linear extrapolations of current trends, like number of functional units.

I think that this incremental research forms one of the key components of the computer architecture research community. First, the research community's ability to place a comprehensive framework and characterization of the problems and solutions forms a basis for much more efficiently addressing the problems, and serve as a foundation for more revolutionary efforts. Second, the level of creativity that can be applied by the research community has invariably led to additional improvements beyond those developed in the corporate labs. Thus, when a new design processor is initiated, a survey of the latest results in a number of areas is conducted to find good design ideas.

The foil to incremental research is revolutionary research. This is research that strikes out in new directions and makes fundamental changes in structures and design assumptions. I feel that the key ingredient in this sort of research is incorporating a view that some cherished assumptions about technological trends or the nature of computing are going to be "broken". It then becomes an object of the research to look for new solutions for that environment. This revolutionary research provides insights and opportunities for creativity that weren't always obvious when following the standard line of progress. The current investigations of processor-in-memory that largely ignores the incompatibilities of CPU and DRAM processes is an example of this assumption "breaking".

The key to revolutionary research being successful is the accuracy of the prediction about which assumptions should be broken as well as the new solutions created. In my experience, however, I've often found that the broken assumptions are not necessarily key to the new knowledge gained, but simply provided a clearer environment for thinking about the solutions.

Contrasting these two types of research, I find that there is great value in incremental research and think that it should be strongly supported. In the context of this workshop, however, I am inclined to derate these as not being "strategic" directions. In military (and often business) parlance a distinction is made between "strategic" or long term activities and "tactical" or short term activities. In these terms, the incremental research activities are fundamentally "tactical" looking to improve existing models rather than striving for the creation of new models as a longer term objective. This leaves revolutionary research as the core for the "strategic" directions for computer architecture.

3 Research Directions

Now that I've established my criteria for judging strategic research directions, I've eliminated the opportunity to take the easiest course which is support for incremental or evolutionary research. I also feel that picking strategic directions for the future should be more than just weighing today's known directions, so I will try to refrain from just picking amongst my current research interests. Instead, with the acknowledged risk that I'm not likely to be radical enough, I will attempt to look at trends that look like they are candidates to have their assumptions broken.

3.1 Support for new applications

First, and probably least surprising is that the state of programs used for doing our evaluations should be updated. We've become complacent in our study of the specmarks and large scientific problems. The computer architecture community has almost completely ignored the increasing importance of multimedia processing including speech, voice recognition, video encode and decode. It should be an embarrassment to the research community that the addition of multimedia instructions has been, to my knowledge, an entirely industrial action without any published evaluation of architectural or algorithmic alternatives by the computer architecture research community.

It is already clear that the behavioral characteristics of large databases; heavily loaded web servers; languages with object oriented, strongly type checked or data integrity orientations, and interpreters, e.g., Java and instruction set emulators are all significantly different from the standard computer architecture paper benchmarks. Examination of the characteristics of these workloads, along with methods for looking at them (as some are very large) should be a fertile area for new architectural innovation.

Note that I'm not calling for the reincarnation of the 432, but probably some RISC-style (or vector) enhancements, or compression techniques that will benefit these programs. Maybe even more significant, new execution models, maybe like simultaneous multithreading or multi-scalar will prove useful.

3.2 Breaking the architecture compact

It has been a longstanding assumption that the architecture forms a binding contract between the compiler (or assembly language programmer) and the micro-architecture or organization of the machine. With increasing processor speeds it is becoming feasible to break this compact and efficiently run code from one architecture on a different architectures. The Digital FX!32 x86 to Alpha system is a early, but effective, example of such a system, as are the schemes for using VLIW code across multiple implementations. If, however, one were to start from the premise that the intermediate form is indeed not directly executed, but is intended to be the run-time compiled to a particular micro-architecture there should be many opportunities for creative research results.

Such an effort requires close cooperation between the compiler and the computer architecture (as was the case for RISC), but could spawn some very interesting innovation in the areas of passing information for more effective code generation to the run-time environment. Such information might include memory aliasing information, performance profile information, and mechanisms for inlining or dealing with shared code libraries.

3.3 Incommensurate technology trends

It has often been correctly cited that computer architecture is a technology driven discipline, and has been the beneficiary of the exponential growth in transistor speed and density that has been characterised as Moore's law. Although there are some indications that manufacturing cost (multi-billion dollar investment in fabs), power, or device characteristics may flatten this growth, to all appearances there is a lot more gas left in these technology trends. Just looking at ways of using this increasing capacity is a challenging research direction.

There appear, however, to already be a number of incommensurate technology trends. Memory speeds have not been changing significantly, and even the pace memory capacity increases have slowed recently. The number of pins have not been increasing exponentially, although flip-chip and other more exotic techniques bode for increased number of pins, maybe with more bandwidth but longer latency. Also there has been some interest in putting logic on DRAMs, maybe foretelling a departure from the dumb memory model to which we've become accustomed. Study of implementation techniques for a carefully selected divergent technology trend, could result in a major new direction for computer architecture.

4.0 Conclusion

I've been told that one of the most accurate methods for forecasting tomorow's weather is to predict that it will be the same as today's weather. Thus while maybe statistically accurate, this technique has the distinct disadvantage that one never predicts changes in the weather and one is never given the opportunity to prepare for change. The same is true of computer architecture. If we never predict and prepare for changes in our assumptions and trends, then we'll never have the opportunity to be proactive in the the research of new and different paradigms.