Computer architecture as a field is undergoing an aging process. Like old dogs not fond of learning new tricks, we in the computer architecture research community have been recycling the same few architectural tricks using a handful of mediocre benchmark suites for the past few decades. Perhaps, most of the blames for turning our field into such a boring and uneventful area should be placed on the tremendous success in IC process and manufacturing technology that strictly followed Moore's Law in the last quarter century. As most indicators point to severe cost burdens for advancing Moore's Law in semicondor manufacturing technology beyond this century, our real challenge just begins.

Computer architecture researchers will face a few serious barriers as we move to the next century:

1)Escalating Power Problem

Traditionally, the power problem is solved by process technology, i.e., each process generation would reduce supply voltage and node capacitance. As voltage cannot be dropped below 1V without other severe complications and as node capacitance reduction reaches a saturation point, there will need to be architecture techniques for reducing power consumption. Unfortunately, most of known techniques, such as cutting back speculation and making buses narrower etc, tend to go against performance goal. A paradigm shift in architecture know-how is needed to reduce power.

2)Worsening Memory Bottleneck

Over the last decades CPU performance improves about 2 orders of magnitude while memory performance, 2X. The widening CPU/memory performance continues which require expensive and intelligent cache-hierarchies to bridge the gap. As more and more evidence point to the inefficiency of caches, our challenge is to understand cache behaviors at a much more detailed level, via classification for example, to gain enough insights to imporve the efficiency. Unfortunately, there is a limit in how far cache hierarchy can be used to bridge the memory gap. The end point solution could call for DRAM and CPU integration. Implications of such an integration will be an active areas for computer architecture research.

3)Daunting Design Complexity

As the number of transistors on a chip keeps growing, so is the size of design teams for microprocessors. Once a design team cannot fit in one floor of a building, troubles begin to creep up.

4)Lack of Fault Tolerancy

As feature size continues to shrink and gate-oxide thickness approaching a few atom height, soft error rate will sky rocket. What to protect and how to protect will be a big issue and only gets bigger.

5)Economy

High-performance may not be the only criteria for future microprocessor products. A majority of world population can probabaly afford other kind of processors than the highest performance one.

In addition to conquering these barriers we should explore a number of promising opportunities:

1) Keep It Simple

2) Go Parallel

3) Work With Apps (In harmony with the environment)

4) Real-time and Consistency

5) Ubiquitous (seamless interoperability)