Sunday
December 10th
8:00 8:45 Invited Talk. Douglas Carmean, Intel, Principal Architect Pentium 4.
8:45 9:05 Morph: Adding an Energy Gear to a High Performance Microarchitecture for Embedded Applications.
P. Kogge, V. Freeh, U. Notre Dame, K. Ghose, SUNY, N. Toomarian, N. Aranki, JPL.
9:05 9:25 Exploiting Bit-Slice Inactivities for Reducing Energy Requirements of Superscalar Processors.
K. Ghose, SUNY.
9:25 9:45 SIMD ISA Extensions: Tradeoffs between Power Consumption and Performance on a Superscalar Processor.
N. Drach and J. Sebot,
10:15 11:00 Invited Talk. Marc Fleischmann,
Director of Low Power Programs, Transmeta Corporation.
11:00 11:20 Dynamic Instruction Scheduling Slack. J. Casmira and D. Grunwald, U. Colorado.
11:20 11:40 A Methodology and Tool Environment for Architectural Level Max Power Estimation and Analysis of Processors.
K. Venkitakrishnan and K. Chen, Hewlett Packard Labs.
11:40 12:00 Invited Talk. Trevor Pering, Microprocessor research Lab, Intel Corporation
1:30 2:15 Invited Talk. Jan Rabaey, UC Berkeley, co-director of the Berkeley Wireless Research Center.
2:15 2:35 Highly-Associative Caches for Low-Power Processors. M. Zhang and K. Asanovic, MIT.
2:35 2:55 Estimation of the Upper-Bound Useless Energy Dissipation in a High-Performance Processor.
E. Musoll, XStream Logic.
2:55 3:15 Low Power Instruction Memoization, D. Citron, IBM Israel, and D. Feitelson, Hebrew U.
3:45 4:05 Adapting Processor Supply Voltage to Instruction-Level Parallelism.
B. Childers, H. Tang, R. Melhem, U. of Pittsburgh.
4:05 4:25 Run-time Scaling of Microarchitecture Resources in a Processor for Energy Savings.
A. Iyer and D. Marculescu, CMU.