Publications: Trevor Mudge

Publications

To appear

Y. Lin,Y. Choi, S.Mahke, S. Mahlke, T. Mudge, and C. Chakrabarti. A parameterized dataflow language extension for embedded streaming systems. SAMOS VIII, July 2008.
E. Ozer, R. Dreslinski, T. Mudge, S. Biles, and K. Flautner. Energy-efficient simultaneous thread fetch from different cache levels in a soft real-time SMT processor. SAMOS VIII, July 2008.
T. Kgil, D. Roberts, T. Mudge. Improving NAND Flash based disk caches. 35th Int. Symp. on Computer Architecture, Beijing, China, June, 2008 .
K. Lim, P. Ranganathan, J. Chang, C. Patel, T. Mudge, S. Reinhardt. Understanding and designing new server architectures for emerging warehouse-computing environments. 35th Int. Symp. on Computer Architecture, Beijing, China, June, 2008.
S. Das, D. Roberts, D. Blaauw, D. Bull, and T. Mudge. Architectural Techniques For Adaptive Computing. In Adaptive Techniques. Eds. A. Wang, and S. Naffziger, Springer.
D. Roberts, N. S. Kim, and T. Mudge. On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology. Jour. Microprocessors and Microsystems.

2008

A. Saidi, N. Binkert, T. N. Mudge, and S. K. Reinhardt. Full System Critical Path Analysis. 2008 IEEE Int. Symp. on Performance Analysis of Systems and Software (ISPASS), April 2008, pp. 63-74.
M. Woh, Y. Lin, S. Seo, T. Mudge, and S. Mahlke. Analyzing the scalability of SIMD for the next generation software defined radio. 33rd Int. Conf. on Acoustics, Speech, and Signal Processing (ICASSP). Las Vegas, April, 2008, pp. 5388-5391.
C. Tokunaga, D. Blaauw, and T. Mudge. True Random Number Generator with a Metastability-based Quality Control. IEEE Jour. Solid-State Circuits, vol. 43, no. 1, Jan. 2008, pp. 78-85.

2007

S. Seo, T. Mudge, Y. Zhu, and C. Chakrabarti. Design and Analysis of LDPC Decoders for Software Defined Radio. 2007 IEEE Workshop on Signal Processing Systems (SiPS 2007), Shanghai, China, Oct. 2007, pp. 210-215.
Y. Lin, M. Kudlur, S. Mahlke, and T. Mudge. Hierarchical Coarse-grained Stream Compilation for Software Defined Radio. Proc. Conf. Compiler and Architecture Support for Embedded Systems (CASES'07), Salzburg, Austria, Oct. 2007, pp. 115-124.
D. Roberts, R. Dreslinski, E. Karl, T. Mudge, D. Sylvester, and D. Blaauw. When Homogeneous becomes Heterogeneous: Wearout Aware Task Scheduling for Streaming Applications. Workshop on Operating System Support for Heterogeneous Multicore Architectures (OSHMA), Romania, Sep. 2007, pp. 5-13.
R. Dreslinski, B. Zhai, T. Mudge, D. Blaauw, and D. Sylvester. An Energy Efficient Parallel Architecture Using Near Threshold Operation. 16th Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), Romania, Sep. 2007, pp. 175-188.
B. Zhai, R. Dreslinski, D. Blaauw, T. Mudge, and D. Sylvester. Energy Efficient Near-threshold Chip Multi-processing. Int. Symp. on Low Power Electronics and Design - 2007 (ISLPED), Aug. 2007, pp. 32-37. [Best Paper Nomination]
D. Roberts, N. S. Kim, and T. Mudge. On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology. DSD 2007 10th EUROMICRO Conf. on Digital System Design. Aug. 2007, Lübeck, Germany.
G. Blake and T. Mudge. Duplicating and Verifying LogTM with OS Support in the M5 Simulator. Workshop on Duplicating, Deconstructing, and Debunking (WDD), held in conjunction with the Int. Symp. on Computer Architecture (ISCA-34), San Diego, CA, June 2007, pp. 23-31.
R. Dreslinski, A. Saidi, T. Mudge, and S. Reinhardt. Analysis of hardware prefetching across virtual page boundaries. ACM Int. Conf on Computing Frontiers, Italy, May 2007, pp. 13-22.
M. Woh, S. Seo, H. Lee, Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti, and K. Flautner. Next Generation Challenge for Software Defined Radio. SAMOS VII, Greece, April 2007, pp. 343-354. [Best Paper]
C. Tokunaga, D. Blaauw, T. Mudge. True random number generator with a metastable-based quality control. Int. Solid-State Circuits Conf. (ISSCC), Feb. 2007, pp. 404-405.
Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner. SODA: A High-Performance DSP Architecture for Software-Defined Radio. IEEE MICRO Top Picks Issue, Jan/Feb. 2007, pp. 114-123.

2006

T. Kgil S. D’Souza A. Saidi N. Binkert, R. Dreslinski S. Reinhardt, K. Flautner, and T. Mudge. PicoServer: Using 3D stacking technology to enable a compact energy efficient chip multiprocessor. 12th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), Nov. 2006, pp. 117-128.
Y. Lin, R. Mullenix, M. Woh, S. Mahlke, T. Mudge, A. Reid, and K. Flautner. SPEX: A programming language for software defined radio. Proc. 2006 SDR Technical Conf., Orlando, FL, Nov. 2006.
H. Lee, C. Chakrabati and T. Mudge. Reducing idle mode power in software defined radio terminals. Int. Symp. on Low Power Electronics and Design - 2006 (ISLPED), Tegernsee, Germany, Oct., 2006, pp. 101-106.
T. Kgil, and T, Mudge. FlashCache: A NAND Flash memory file cache for low power web servers. Proc. Conf. Compiler and Architecture Support for Embedded Systems (CASES'06), Seoul, S. Korea, Oct. 2006, pp. 103-112.
Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti, A. Reid, and K. Flautner. Design and implementation of Turbo decoders for software defined radio. IEEE 2006 Workshop on Signal Processing Systems (SiPS'06), Banff, Canada, Oct. 2006, pp. 22 - 27.
Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, K Flautner. SODA: A low-power architecture for software radio. Proc. 33rd Ann. Int. Symp. on Computer Architecture, Boston, MA USA, June 2006, pp. 89-101. [Top Pick—selected as one of the 12 best papers in computer architecture for 2006]
E. Karl, D. Sylvester, D. Blaauw, and T. Mudge. Reliability modeling and management in dynamic microprocessor-based systems. Proc. of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2006, pp. 1057-1060.
S. Plaza, I. Kountanis, Z. Andraus, V. Bertacco, T. Mudge. Advances and insights into parallel SAT solving. Int. Workshop on Logic and Synthesis (IWLS), June 2006, pp. 188-194.
A. Jerraya, and T. Mudge. Guest editorial: Concurrent hardware and software design for multiprocessor SoC. ACM Trans. on Embedded Computing Systems, vol. 5, no. 2, May 2006, pp. 259–262.
S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, T. Mudge, K. Flautner. A self-tuning dynamic voltage scaled processor using delay-error detection and correction. IEEE Int. Conf. on Integrated Circuit Design and Technology (ICICDT '06), Padova, Italy, May 2006, pp.211-214.
S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, T. Mudge. A self-tuning DVS processor using delay-error detection and correction. IEEE Jour. Solid-State Circuits, vol. 41, no. 4, April 2006, pp. 792-804.

2005

Y. Lin, H. Lee, Y. Harel, M. Woh, N. Baron, S. Mahlke, T. Mudge, and K. Flautner. A system solution for high-performance, low-power SDR. Proc. 2005 SDR Technical Conf., Annaheim, CA, Nov. 2005, 6 pp.
H. Lee, Y. Lin, Y. Harel, M. Woh, S. Mahlke, T. Mudge, and K. Flautner. Software defined radio—A high performance embedded challenge. Proc. 1st Int. Conf. High Performance Embedded Architectures and Compilers (HiPEAC'05), Barcelona, Spain, Nov. 2005. Eds. T. Conte, N. Navarro, W. W. Hwu, M. Valero, T. Ungerer. Lecture Notes in Computer Science, Springer-Verlag GmbH, vol. 3793 / 2005, pp. 6-26.
D. Oehmke, N. Binkert, T. Mudge, and S. Reinhardt. How to fake 1000 registers. Proc. 38th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-36), Nov. 2005, pp. 7-18. [Best Paper Nomination] (original pdf)
N. S. Kim, T. Kgil, K. Bowman, V. De, and T. Mudge. Total power-optimal pipelining and parallel processing under process variations in nanometer technology. Proc. Int. Conf. of Computer Aided Design (ICCAD-2005), Nov. 2005, pp. 535-540. (original pdf)
N. S. Kim, D. Blaauw, and T. Mudge. Quantitative analysis and optimization techniques for on-chip cache leakage power. IEEE Trans. VLSI, vol. 13, no. 10, Oct. 2005, pp.1147-1156.
H. Lee, and T. Mudge. A dual processor solution for the MAC layer of a software defined radio terminal. Proc. Conf. Compiler and Architecture Support for Embedded Systems (CASES'05), Sep. 2005, CA, pp. 257-265.
T. Mudge. Introduction to the special issue of the IEEE Trans. Computers on Energy Efficient Computing, vol. 54, no. 6, June 2005, pp. 641-641.
W. Shi, H.-H. Lee, G. Gu, M. Ghosh, L. Falk, and T. Mudge. Intrusion tolerant and self-recoverable network service system using security enhanced chip multiprocessors. Proc. of the 2nd Int. Conf. on Autonomic Computing, Seattle, Washington, June 2005. (original pdf)
S. Das, S. Pant, D. Roberts, S. Lee, D. Blaauw, T. Austin, T. Mudge, and K. Flautner. Razor: A self-tuning DVS processor using delay-error detection and correction. 2005 Symposium on VLSI Circuits, Kyoto, Japan, June 2005, pp. 258-261. (original pdf)
R. Bai, N. S. Kim, D. Sylvester, and T. Mudge. Total leakage optimization strategies for multi-level caches. ACM/IEEE Great Lakes Symposium on VLSI, 2005, pp. 381-384. (original pdf)
D. Roberts, T. Austin, D. Blaauw, and T. Mudge. Error analysis for the support of robust voltage scaling. Proc. 6th Int. Symp. on Quality Electronic Design (ISQED), March 2005, pp. 65-70. (original pdf)
J. Ringenberg, C. Pelosi, D. Oehmke, and T. Mudge. Intrinsic checkpointing: A methodology for decreasing simulation time through binary modification, Proc. of the IEEE Int. Symp. on Performance Analysis of Systems and Software(ISPASS), March 2005, Austin, TX, pp. 78-88. (original pdf)
A. Cheng, G. Tyson, T. Mudge. PowerFITS: Reduce Dynamic and Static I-cache power using application specific instruction set synthesis. Proc. of the IEEE Int. Symp. on Performance Analysis of Systems andSoftware (ISPASS), March 2005, Austin, TX, pp. 32-41. (original pdf)
R. Bai, Nam Sung Kim, T. Mudge, and D. Sylvester. Power-performance trade-offs in nanometer-scale multi-level caches considering total leakage. Proc. Design, Automation and Test in Europe (DATE), Munich, March 2005, pp. 650-651. (original pdf)
H. Kaul, D. Sylvester, D. Blaauw, T. Mudge, and T. Austin. DVS for on-chip bus designs based on timing error correction. Proc. Design, Automation and Test in Europe (DATE), Munich, March 2005, pp. 80-85. (original pdf)
T. Austin, V. Bertacco, D. Blaauw, and T. Mudge. Opportunities and challenges for better than worst case design. Proc. Asia South Pacific Design Automation Conf. (ASP-DAC), Shanghai, China, vol. 1, Jan. 2005 pp. I/2-I/7. (original pdf)

2004

D. Ernst, S. Das, S. Lee, D. Blaauw, T. Austin, T. Mudge, N. S. Kim, and K. Flautner. Razor: circuit-level correction of timing errors for low-power operation. IEEE MICRO, vol. 24, no. 6, Nov./Dec. 2004, pp.10-20. Selected as a "Top pick" from the top microarchitecture conferences of 2003/4 (Micro-36, HPCA 10, ISCA 31,PACT 2004, ASPLOS XI). [pdf]
Y. Lin, N. Baron, H. Lee, S. Mahlke, and T. Mudge. A programmable vector coprocessor architecture for wireless applications. Proc. 3rd Workshop on Application Specific Processors (WASP), in conjunction with the Int. Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Stockholm, Sweden, Sep. 2004, pp. 103-110. [pdf]
T. Kgil, L. Falk, and T. Mudge. ChipLock: Support for Secure Microarchitectures. Proc. Workshop on Architectural Support for Security and Anti-virus (WASSA), in conjunction with 11th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-XI), , Boston, MA, Oct. 2004, pp. 130-139. [pdf]
N. Kim and T. Mudge. Single Vdd and single Vt super-drowsy techniques for low-leakage high-performance instruction caches. Proc. of the Int. Symp. on Low Power Electronics and Design (ISLPED), Newport Beach, CA, Aug. 2004, pp. 54-57. [pdf]
S. Lee, T. Austin, D. Blaauw, and T. Mudge. Reducing pipeline energy demands with local DVS and dynamic retiming. Proc. of the Int. Symp. on Low Power Electronics and Design (ISLPED), Newport Beach, CA, Aug. 2004, pp. 319-324 [pdf]
N. Kim, T. Kgil, V. Bertacco, T. Austin, and T. Mudge. Microarchitectural power modeling techniques for deep sub-micron microprocessors. Proc. of the Int. Symp. on Low Power Electronics and Design (ISLPED), Newport Beach, CA, Aug. 2004, pp. 212-217. [pdf]
S. Lee, S. Das, V. Bertacco, T. Austin, D. Blaauw, and T. Mudge. Circuit-aware architectural simulation. Proc. of the ACM/IEEE Design Automation Conference (DAC), San Diego, CA, June 2004, pp. 305-310. [pdf]
A. Cheng, G. Tyson, and T. Mudge. FITS: Framework-based instruction-set tuning synthesis for embedded application specific processors. Proc. of the ACM/IEEE Design Automation Conference (DAC), San Diego, CA, June 2004, pp. 920-923. [pdf]
T. Austin, D. Blaauw, S. Mahlke, and T. Mudge, and C. Chakrabati, and W. Wolf. Mobile Supercomputers. Comm. of the ACM, vol. 37, no. 5, May, 2004, pp. 81-83. [pdf]
A. Cheng, G. Tyson, and T. Mudge. FITS: Increasing code density for embedded systems with a cost-effective 16-bit ISA synthesis technique. 2nd IEEE/ACM Workshop on Optimizations for DSP and Embedded Systems (ODES), in conjunction with the Int. Symp. on Code Generation and Optimization (CGO), San Jose, CA, Mar. 2004, [pdf]
T. Austin, D. Blaauw, T. Mudge, and K. Flautner. Making Typical Silicon Matter with Razor. Computer, vol. 37, no. 3, Mar. 2004, pp. 41-49. [pdf]
N. Kim, K. Flautner, D. Blaauw, and T. Mudge. Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans. VLSI, vol. 12, no. 2, Feb. 2004, pp. 167-184. [pdf]

2003

Nam Sung Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner , J. Hu, M. Irwin, M. Kandemir, N. Vijaykrishnan. Leakage Current: Moore's Law Meets Static Power. Computer, vol. 36, no. 12, Dec. 2003, pp. 65-77. [pdf]
J. Ringenberg, D. Oehmke, T. Austin, and T. Mudge. SimpleDSP: A Fast and Flexible DSP Processor Model. 5th Workshop on Media and Streaming Processors (MSP5) in the 36th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-36), Dec. 2003. [pdf]
D. Ernst, N. Kim, S. Das, S. Pant, T. Pham, R. Rao, C. Ziesler, D. Blaauw, T. Austin, T. Mudge, and K. Flautner. Razor: A low-power pipeline based on circuit-level timing speculation. 36th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-36), Dec. 2003, pp. 7-18. [received best paper award]. [pdf]
N. Kim, D. Blaauw, and T. Mudge. Leakage power optimization techniques for ultra deep sub-micron multi-level caches. Proc. Int. Conf. of Computer Aided Design (ICCAD-2003), San Jose, CA, Nov. 2003, pp. 627-632. [pdf]
N. Kim, T. Mudge, and R. Brown. A 2.3Gb/s fully integrated and synthesizable AES Rijndael core. Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2003, pp. 193-196. [pdf]
N. Kim and T. Mudge. Microarchitecture for a low power register file with reduced register ports. Proc. of the Int. Symp. on Low Power Electronics and Design (ISLPED), Seoul, Korea, Aug. 2003, pp. 384-389. [pdf]
N. Kim and T. Mudge. Reducing register ports using delayed write-back queues and operand pre-fetch. Proc. of the Int. Supercomputing Conf., San Francisco, CA, June 2003, pp. 172-182. [pdf]
G. Gao and T. Mudge. Special Issue on Compilers, Architecture, and Synthesis for Embedded Systems. ACM Trans. Embedded Computer Systems, vol. 2, no. 2, May 2003. [pdf]

2002

K. Flautner and T. Mudge. Vertigo: Automatic performance-setting for Linux. Proc. of the 5th Operating Systems Design and Implementation (OSDI), Dec. 2002, pp. 105-116. [pdf]
D. Blaauw, S. Martin, T. Mudge, K. Flautner. Leakage current reduction in VLSI systems. Jour. of Circuits, Systems, and Computers, 11(6), 2002, pp. 621-636. [pdf]
N. Kim, K. Flautner, D. Blaauw, and T. Mudge. Drowsy instruction caches: Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. 35th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-35), Nov. 2002, pp. 219-230.[pdf]
S. Martin, K. Flautner, D. Blaauw, and T. Mudge. Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. Proc. Int. Conf. of Computer Aided Design (ICCAD-2002), San Jose, CA, Nov. 2002, pp. 721-725. [pdf]
K. Flautner, S. Reinhardt, and T. Mudge. Automatic performance setting for dynamic voltage scaling. ACM Jour. Wireless Networks, vol. 8, no. 5, Sep. 2002, pp. 507-520. [pdf]
K. Flautner, N. Kim, S. Martin, D. Blaauw, T. Mudge. Drowsy Caches: Simple techniques for reducing leakage power. Proc. of the 29th Ann. Int. Symp. on Computer Architecture, Anchorage Alaska, May 2002, pp. 148-157. [pdf]
N. Kim, T. Austin, and T. Mudge. Low-energy data cache using sign compression and cache line bisection. 2nd Annual Workshop on Memory Performance Issues (WMPI). In conjunction with the 29th Ann. Int. Symp. on Computer Architecture, Anchorage Alaska, May 2002, pp. [pdf]

2001

N. Kim, T. Austin, T. Mudge, and D. Grunwald. Challenges for architectural level power modeling. in Power Aware Computing, (R. Melhem and R. Graybill eds.), Kluwer Academic Publishers: Boston, MA, 2001. [pdf]
M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown. MiBench: A free, commercially representative embedded benchmark suite. IEEE 4th Annual Workshop on Workload Characterization, (held in conjunction with 34th Ann. IEEE/ACM Symp. Microarchitecture, Austin, TX), Dec. 2001, pp. 3-14. [pdf]
V. Cuppu, B. Jacob, B. Davis, and T. Mudge. High-performance DRAMs in workstation environments. IEEE Trans. Computers, vol. 50, no. 11, Nov. 2001, pp. 1133-1153. [pdf]
K. Flautner, S. Reinhardt, and T. Mudge. Automatic performance setting for dynamic voltage scaling. Proc. 7^th Ann. Int. Conf. On Mobile Computing and Networking (MOBICOM), Rome, Italy, July 2001, pp. 260-271. [pdf]
A. Eden, J. Ringenberg, S. Sparrow, and T. Mudge. Hybrid myths in branch prediction. Proc. 5th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001) and the 7th Int. Conf. on Information Systems Analysis and Synthesis (ISAS 2001), vol. XIV, Comp.Sci. & Engineering, Orlando, FL, July 2001, pp. XIV 74-81. [pdf]
M. Postiff, D. Greene, S. Raasch, and T. Mudge. Integrating superscalar processor components to implement register caching. Proc. 15th ACM Int. Conf. On Supercomputing (ICS'01), Sorrento, Italy, June 2001, pp. 348-357. [pdf file]
B. Jacob and T. Mudge. Uniprocessor virtual memory without TLBs. IEEE Trans. Computers, vol. 50, no. 5, May 2001, pp. 482-499. [pdf file]
T. Mudge. Power: A first class design constraint. Computer, vol. 34, no. 4, April 2001, pp. 52-57. [pdf file]

2000

T. Mudge. Power: A first class design constraint for future architectures. Proc.7th Int. Conf. on High Performance Computing - HiPC, (Springer Lecture Notes in Computer Science), Dec. 2000, Bangalore, India, pp. 215-224. [pdf file]
M. Postiff, D. Greene, and T. Mudge. The store-load address table and speculative register promotion. 33rd Ann. IEEE/ACM Symp. Microarchitecture (MICRO-33), Dec. 2000, pp. 235-244. [pdf file]
D. Van Campenhout, T. Mudge, and J. P. Hayes. Collection and analysis of microprocessor design errors. IEEE Design & Test, 17(4), Oct.-Dec., pp. 51-60. [pdf file]
K. Flautner, S. Reinhardt, and T. Mudge. Thread-level parallelism and interactive performance of desktop applications. 9th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-IX), Nov. 2000, pp. 129-138. [pdf]
B. Davis, B. Jacob, and T. Mudge. The new DRAM interfaces: SDRAM, RDRAM and variants. 3rd Int. Symp. High Performance Computing, Lecture Notes in Computer Science, M. Valero, K. Joe, M. Kitsuregawa, and H. Tanaka, Editors, vol. 1940, Publ: Springer, Tokyo, Japan, Oct. 2000, pp. 26-31. [pdf]
B. Davis, T. Mudge, and B. Jacob. DDR2 and low latency variants.Proc. Memory Wall Workshop. In conjunction with the 26th Ann. Int. Symp. Computer Architecture, May 2000. [pdf file]
A. Eden, B. Joh, T. Mudge. Web latency reduction via client-side prefetching. Proc. 2000 IEEE Int. Symp. on Performance Analysis of Systems & Software (ISPASS-2000), Austin, TX, April 2000, pp. 193-200. [pdf file]
K. Flautner, R. Uhlig, S. Reinhardt, and T. Mudge. Thread level parallelism of desktop applications. Proc. Workshop on Multi-threaded Execution, Architecture and Compilation (MTEAC2000). In conjunction with the 6th Int. Symp. on High Performance Computer Architecture (HPCA-6), Toulouse France, Jan. 2000. [pdf file]
C. Lefurgy, E. Piccininni, T. Mudge. Reducing code size with run-time decompression. Proc. of the 6th Int. Symp. on High-Performance Computer Architecture, Jan. 2000, pp. 218-227. [pdf file]

1999

R. Uhlig and T. Mudge. Trace-driven memory simulation: A survey. in Performance Evaluation: Origins and Directions. Eds. G. Haring, C. Lindemann, and M. Reiser Lecture Notes in Computer Science, Springer-Verlag, 1999, pp. 97-139.[pdf file] [Abridged from ACM Computing Surveys, vol. 29, no, 2, June 1997, pp. 128-170.]
D. Van Campenhout, T. Mudge, and J. P. Hayes. Error simulation with conditional error models. Proc. 4th IEEE Int. High Level Design Validation and Test Workshop, La Jolla CA, Nov. 1999, pp. 198-205. [pdf file]
C. Lefurgy, E. Piccininni, T. Mudge. Evaluation of a high performance code compression method. Proc.of the 32nd Ann. Symp. on Microarchitecture, Nov. 1999, pp. 93-102. [pdf file]
M. Postiff, G. Tyson, T. Mudge. Performance limits of trace caches. Jour. Instruction Level Parallelism, Oct. 1999. [pdf file]
C. Lefurgy, T. Mudge. Fast software-managed code decompression. 2nd Int. Workshop on Compiler and Architecture Support for Embedded Systems (CASES99), Oct. 1999, pp. 139-143 . [pdf file]
D. Van Campenhout, T. Mudge, and J. P. Hayes. High-level test generation for design verification of pipelined microprocessors. Proc. of the 36th ACM/IEEE Design Automation Conf., New Orleans, June 1999, pp. 185-188. [pdf file]
V. Cuppu, B. Jacob, B. Davis, T. Mudge. A performance comparison of contemporary DRAM architectures. Proc. of the 26th Ann. Int. Symp. Computer Architecture, May 1999, pp. 222-233. [pdf file]
D. Van Campenhout, T. Mudge, and K. Sakallah. Timing verification of sequential dynamic circuits. IEEE Trans. Computer-Aided Design, vol. 18, no. 5, May 1999, pp. 645-658. [pdf file]
M. Postiff, D. Greene, G. Tyson, and T. Mudge. The limits of instructions level parallelism in SPEC95 applications. Computer Architecture News, vol. 27, no. 1, March 1999, pp. 31-34. Condensed from Proc. 3rd Workshop on Interaction Between Compilers and Computer Architecture (INTERACT-3) at the 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct. 1998. [pdf file]
K. Flautner, G. Tyson, and T. Mudge. MIRVSim: a high level simulator integrated with the MIRV compiler. Computer Architecture News, vol. 27, no. 1, March 1999, pp. 43-46. Condensed from Proc. 3rd Workshop on Interaction Between Compilers and Computer Architecture (INTERACT-3) at the 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct. 1998. [pdf file]
H. Al-Asaad, J. Hayes, T. Mudge. Modeling and detecting control errors in microprocessors. Int. IEEE Conf. on DYnamic CONtrol Systems (DYCONS-99). [pdf]

1998

A. Eden, and T. Mudge. The YAGS branch predictor. 31th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-31), Dec. 1998, pp. 69-77. [pdf file]
C. Lefurgy, and T. Mudge. Code compression for DSP. 2nd Int. Workshop on Compiler and Architecture Support for Embedded Systems (CASES98), 3(4), Dec. 1998. [pdf file]
D. Van Campenhout, T. Mudge, and J. P. Hayes. High-level test generation for design verification of pipelined microprocessors. Proc. 3rd IEEE Int. High Level Design Validation and Test Workshop, La Jolla CA, Nov. 1998, pp.1-8. [pdf file]
D. Van Campenhout, H. Al-Asaad, J. P. Hayes, T. Mudge, and R. Brown. High-level design verification of microprocessors via error modeling. ACM Trans. on Design Automation of Electronic Systems, 3(4), Oct. 1998, pp. 581-599. [pdf file]
D. Van Campenhout, T. Mudge, and J. P. Hayes. Evaluation of design error models for verification testing of microprocessors. Proc. IEEE 1st Int. Workshop on Microprocessor Test and Verification, Washington DC, Oct. 1998. [pdf file]
B. Jacob, and T. Mudge. A look at several memory management units, TLB-refill mechanisms, and page table organizations. 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), San Jose CA, Oct. 1998, pp. 295-306. [pdf file]
K. Flautner, G. Tyson, and T. Mudge. MIRVSim: a high level simulator integrated with the MIRV compiler. Proc. 3rd Workshop on Interaction Between Compilers and Computer Architecture (INTERACT-3). In conjunction with the 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct. 1998. [pdf file]
D. Burger, G. Tyson, T. Austin, J. Smith, and T. Mudge. Alcohol Content vs. Flavor: A Case Study. Zymurgy Magazine. Oct. 1998.
M. Postiff, D. Greene, G. Tyson, and T. Mudge. The limits of instructions level parallelism in SPEC95 applications. Proc. 3rd Workshop on Interaction Between Compilers and Computer Architecture (INTERACT-3). In conjunction with the 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct. 1998. [pdf file]
K. Flautner and T. Mudge. Introspective computers. Proc. Wild and Crazy Ideas Session. In conjunction with the 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct. 1998. [pdf file]
B. Jacob, and T. Mudge. Virtual memory in contemporary microprocessors. Micro, vol. 18, no. 4, pp. 60-75. July/Aug. 1998. [pdf file]
C-C. Lee, I-C. Chen, and T. Mudge. Design and performance evaluation of global history dynamic branch predictors. Proc. World Multiconference on Systemics Cybernetics and Informatics, SCI'98, (and, the 4th International Conference on Information Systems Analysis and Synthesis - ISAS98), vol. 2, Orlando, FL, July 1998, pp. 664-671. [pdf file]
B. Jacob, and T. Mudge. Virtual memory: Issues of implementation. Computer, vol. 31, no. 6, pp. 33-43. June 1998. [pdf file]
R. Brown, B. Bernhardt, M. LaMacchia, J. Abrokwah, P. Parakh, T. Basso, S. Gold, S. Stetson, C. Gauthier, D. Foster, B. Crawforth, T. McQuire, K. Sakallah, R. Lomax, T. Mudge. Overview of complementary GaAs technology for high-speed VLSI circuits. IEEE Trans. VLSI, vol. 6, no. 1, March 1998, pp. 47-51.[pdf file]

1997

M. Kelley, M. Postiff, T. Strong, R. Brown, and T. Mudge. A complementary GaAs 32-bit multiply-accumulate unit. 31st Asilomar Conference on Signals, Systems, and Computers, Nov. 1997, pp. 1507-1511. [pdf file]
H. Al-Asaad, D. Van Campenhout, J. Hayes, T. Mudge. High-level design verification of microprocessors via error modeling. Proc. IEEE Int. Workshop on High Level Design Validation and Test, Nov. 1997, pp. 194-201. [pdf file]
C. Lee, I. Chen, and T. Mudge. The bi-mode branch predictor. 29th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-29), Dec. 1997, pp. 4-13. [pdf file]
C. Lefurgy, P. Bird, I-C. Cheng, T. Mudge. Improving code density using compression techniques. 29th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-29), Dec. 1997, pp. 194-203. [pdf file]
O. Olukotun, T. Mudge, R. Brown. Performance optimization of pipelined caches. IEEE Trans. Computers, vol. 46, no. 10, Oct. 1997, pp. 1093-1102. [pdf file]
I-C. Chen, C-C. Lee, and T. Mudge. Instruction prefetching using branch prediction information. Int. Conf. Computer Design 97, Oct. 1997, pp. 593-601. [pdf file]
I-C. Chen, C-C. Lee, M. Postiff, and T. Mudge. Design optimization for high-speed per-address two-level branch predictors. Int. Conf. Computer Design 97, Oct. 1997, pp. 88-96. [pdf file]
James Dundas and Trevor Mudge. Improving data cache performance by pre-executing instructions under a cache miss. Proc. 1997 ACM Int. Conf. on Supercomputing, July 1997, pp. 68-75.[pdf file]
R. Uhlig and T. Mudge. Trace-driven memory simulation: A survey. ACM Computing Surveys, vol. 29, no, 2, June 1997, pp. 128-170. [pdf file]
B. Davis, C. Gauthier, P. Parakh, T. Basso, C. Lefurgy, R. Brown, and T. Mudge. Impact of MCMs on high performance processors. Proc. ASME Advances in Electronic Packaging 97 vol. 1 (EEP-vol. 19-1), June 1997, pp. 863-868. [pdf file]
B. L. Jacob and T. Mudge. Software-managed address translation. Proc. 3rd Symp. High Performance Computer Architecture, San Antonio, TX, Feb. 1997, pp. 156-167. [pdf file]
R. Uhlig, D. Nagle, T. Mudge and S. Sechrest. Trap-driven memory simulation with Tapeworm II. ACM Trans. Modeling and Computer Simulation (TOMACS), vol. 7, no. 1, Jan. 1997, pp. 7-41. [pdf file]

1996

T. Mudge. Strategic directions in computer architecture. ACM Computing Surveys, vol. 28, no. 4, Dec. 1996, pp. 671-678. [pdf file] Also available online to Surveys subscribers via the URL http://www.acm.org/pubs/contents/journals/surveys/1996-28/#4
R. Brown, T. Basso, P. Parakh, S. Gold, C. Gauthier, R. Lomax, and T. Mudge. Complementary GaAs technology for a GHz microprocessor. Tech. Digest of the GaAsIC Symp., Nov. 1996, pp. 313-316. [pdf file]
D. Van Campenhout, T. Mudge, and K. Sakallah. Timing verification of sequential domino circuits. Proc. Int. Conf. CAD, Dec. 1996 , pp. 127-132.[pdf file]
J. Pierce and T. Mudge. Wrong path instruction prefetching. 29th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-29), Dec. 1996, pp. 165-175. [pdf file]
B. L. Jacob and T. Mudge. Support for nomadism in a global environment. Workshop on Object Replication and Mobile Computing, San Jose, CA, Oct., 1996. Electronic document. [pdf file]
B. L. Jacob and T. Mudge. The trading function in action. Proc. 7th ACM SIGOPS European Workshop, Connemara, Ireland, Sep. 1996, pp. 241-247. [pdf file]
D. Van Campenhout, T. Mudge, and K. Sakallah. Timing verification of sequential domino circuits. Proc. TechCon 96, Sep. 1996, available as an electronic document to members of Semiconductor Research Corp.[pdf file]
I-C. Cheng, J. Coffey, and T. Mudge. Compression and branch prediction. 7th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), Oct. 1996, pp. 128-137. [pdf file]
R. Brown, J. Hayes, and T. Mudge. Rapid prototyping & evaluation of high-performance computers. Proc. Conf. Experimental Research in Computer Systems, NSF Experimental Systems, Ed. L. Snyder, Washington DC, June 1996, pp. 159-168. [pdf file]
T. Mudge. Position paper: NSF Workshop on Critical Issues in Computer Architecture Research, May 1996. Electronic document
Trevor Mudge. Panel report: "How can computer architecture researchers avoid becoming the society for irreproducible results?" Computer Architecture News, vol. 24, no. 1, March 1996, pp. 1-5. [pdf file]
B. Jacob, P. Chen, S. Silverman, T. Mudge. An analytical model for designing memory hierarchies. IEEE Trans. Computers, vol. 45, no. 10, Oct. 1996, pp. 1180-1194. [pdf file]
Michael Golden and Trevor Mudge. A comparison of two common pipeline structures. Institution of Electrical Engineers Proc.-E, Computers and Digital Techniques, vol. 143, no. 3, May 1996.
S. Sechrest, C-C. Lee, T. Mudge. Correlation and aliasing in dynamic branch predictors. Proc. of the 23rd Ann. Int. Symp. Computer Architecture, May 1996, pp. 22-32. [pdf file]

1995

S. Sechrest, C-C. Lee, T. Mudge. The role of adaptivity in two-level branch prediction. 28th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-28), Dec. 1995, pp. 264-270. [pdf file]
J. Pierce, M. D. Smith, and T. Mudge. Instrumentation tools. in Fast Simulation of Computer Architectures (T. M. Conte and C. E. Gimarc, eds.), Kluwer Academic Publishers: Boston, MA, 1995, pp. 47-86. [pdf file]
T. J. Stanley and T. Mudge. A parallel genetic algorithm for multi-objective microprocessor design. Proc. of ICGA-95: 6th Int. Conf. Genetic Algorithms, July 1995, pp. 597-604.
R. Uhlig, D. Nagle, T. Mudge, S. Sechrest, and J. Emer. Instruction fetching: Coping with code bloat. Proc. of the 22nd Ann. Int. Symp. Computer Architecture, June 1995, pp. 345- 356. [pdf file]
K. Sakallah, T. Burks, and T. Mudge. Critical paths in circuits with level-sensitive latches. IEEE Trans. VLSI Systems, vol. 3, no. 2, June 1995, pp. 273-291.
Brian Davis and Trevor Mudge. A Verilog preprocessor for representing datapath components. Proc. 4th Int. Verilog HDL Conf., Mar. 1995, pp. 90-98. [pdf file]
T. J. Stanley and T. N. Mudge. A systematic approach to multi-objective computer architecture optimization. 1995 Conf. Advanced Research in VLSI, March 1995, pp. 286-300.

1994

D. Nagle, R. Uhlig, T. Stanley, T. Mudge, S. Sechrest and R. Brown. Design trade-offs for software-managed TLBs. ACM Trans. Computer Systems, vol. 12, no. 3, Aug. 1994, pp. 175-205.
Michael Golden and Trevor Mudge. A comparison between two pipeline organizations. 27th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-27), Dec. 1994, pp. 153-161. [pdf file]
R. Uhlig, D. Nagle, T. Mudge, and S. Sechrest. Trap-driven simulation with Tapeworm II. 6th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VI), Oct. 1994, pp. 132-144. [pdf file]
M. Upton, T. Huff, T. Mudge, and R. Brown. Resource allocation in a high clock rate microprocessor. 6th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VI), Oct. 1994, pp. 98-109.
D. Nagle, R. Uhlig, T. Mudge, and S. Sechrest. Kernel-based memory simulation. ACM SIGMETRICS Conf. Measurement and Modeling of Computer Systems, May 1994, pp. 286-287. [pdf file]
Jim Pierce and Trevor Mudge. The effect of speculative execution on cache performance. IPPS 94, Int. Parallel Processing Symp., Cancun Mexico, Apr. 1994, pp. 172-179. [pdf file]
D. Nagle, R. Uhlig, T. Mudge, and S. Sechrest. Optimal allocation of on-chip memory for multiple-API operating systems. Proc. of the 21st Ann. Int. Symp. Computer Architecture, Apr. 1994, pp. 358-369. [pdf file]
Jim Pierce and Trevor Mudge. IDtrace - A tracing tool for i486 simulation. MASCOTS, Jan.- Feb. 1994, pp. 419-420. [pdf file]

1993

T. Stanley, M. Upton, P. Sherhart, T. Mudge, R. B. Brown. A microarchitectural performance evaluation of a 3.2 GB/s microprocessor bus. The Ann. ACM/IEEE Int. Symp. Microarchitecture, MICRO-26, Austin, TX, Dec. 1993, pp. 31-40.
R. Brown, M. Upton, A. Chandna, T. Huff, T. Mudge, and R. Oettel. Gallium arsenide process evaluation based on a RISC microprocessor example. IEEE Jour. Solid-State Circuits, vol. 28, no. 10, Oct. 1993, pp. 1030-1037.
K. Sakallah, T. Mudge, T. Burks, and E. Davidson. Synchronization of pipelines. IEEE Trans. CAD of IC's and Systems, vol. 12, no. 8, Aug. 1993, pp. 1132-1146.
T. Huff, M. Upton, T. Mudge, R. Brown. The Aurora project. Record of Hot Chips V, Aug. 1993, pp. 3.2.1 - 3.2.12.
D. Nagle, R. Uhlig, T. Stanley, T. Mudge, S. Sechrest and R. Brown. Design tradeoffs for software-managed TLBs. Proc. of the 20th Ann. Int. Symp. Computer Architecture, May 1993, pp. 27-38. [pdf file]
A. Kayssi, T. Mudge, and K. Sakallah. The impact of signal transition time on path delay computation. IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 40, no. 5, May 1993, pp. 302-309.
T. Huff, M. Upton, P. Sherhart, P. Barker, R. McVay, T. Stanley, R. Brown, R. Lomax, T. Mudge, and K. Sakallah. A high performance GaAs microprocessor. Proc. IEEE Laser and Optics Soc. Sarnoff Symp., Princeton, Mar. 1993, no page no.
M. Upton, T. Huff, P. Sherhart, P. Barker, R. McVay, T. Stanley, R. Brown, R. Lomax, T. Mudge, and K. Sakallah. A 160,000 transistor GaAs microprocessor. Int. Solid-State Circuits Conf. Digest of Technical Papers, vol. 36, Feb. 1993, pp. 92-93.

1992

R. Brown, P. Barker, A. Chandna, T. Huff, R. Lomax, T. Mudge, K. Sakallah, P.J. Sherhart, R. Uhlig, and M. Upton. GaAs RISC processors. GaAs IC Symp., Miami, Oct. 1992, pp. 81-84.
R. Brown, A. Chandna, T. Huff, R. Lomax, T. Mudge, R.Oettel, and M. Upton. Compound semiconductor device requirements for VLSI. Proc. 19th Int. Symp. GaAs and Related Compounds, (Institute of Physics Conf. Series No. 129), Karuizawa, Japan, Oct. 1992, pp. 857-862.
T. Burks, K. Sakallah, and T. Mudge. Critical paths through level-sensitive latches. Int. Conf. CAD, Nov. 1992, pp. 137-141.
R. Brown, A. Chandna, T. Hoy, T. Huff, D. Johnson, R. Lomax, T. Mudge, D. Nagle, O. Olukotun, K. Sakallah, R. Uhlig, and M. Upton. Synthesis and verification of a GaAs microprocessor from a Verilog hardware description. Proc. Open Verilog Int. User Group Meeting, Mar. 1992, pp. 85-93.
T. Burks, K. Sakallah, and T. Mudge. Multi-phase retiming using minTc. TAU 92: 1992 ACM/SIGDA W/shop Timing Issues in the Specification and Synthesis of Digital Systems, Princeton Univ., Mar. 1992, 10 pp.
O. Olukotun, T. Mudge, and R. Brown. Performance optimization of pipelined primary caches. Proc. 19th Ann. Int. Symp. Computer Architecture, May 1992, pp. 181-190.
A. Kayssi, K. Sakallah, R. Brown, R. Lomax, T. Mudge, and T. Huff. Impact of MCMs on system performance optimization. 1992 IEEE Int. Symp. Circuits and Systems, vol. 2 of 6, San Diego, CA, May 1992, pp. 919-922.
R. Clapp and T. Mudge. Parallel language constructs for efficient parallel processing. Proc. Hawaii Int. Conf. System Sciences, Jan. 1992, pp. 230-241.
K. Sakallah, T. Mudge, and O. Olukotun. Analysis and design of latch-controlled synchronous digital circuits. IEEE Trans. CAD of ICs and Systems, vol. 11, no. 3, Mar. 1992, pp. 322-333.
A. Ladd, T. Mudge, and O. Olukotun. Measuring process migration effects using an MP simulator. Scalable Shared Memory Multiprocessors, Ed. M. Dubois and S. Thakkar, Kluwer Academic Publ., 1992, pp. 97-129.

1991

K. Sakallah, T. Mudge, T. Burks, and E. Davidson. Optimal clocking of circular pipelines. Proc. Int. Conf. Computer Design: VLSI in Computers and Processors, Oct. 1991, pp. 642-646.
A. Kayssi, K. Sakallah, R. Brown, R. Lomax, T. Mudge, and T. Huff. Impact of MCMs on system performance. 1991 Multichip Module Workshop, University of California, Santa Cruz, March 1991, pp. 58-65.
O. Olukotun, T. Mudge, and R. Brown. Implementing a cache for a high-performance GaAs microprocessor. Proc. of the 18th Ann. Int. Symp. Computer Architecture, May 1991, pp. 138-147.
O. Olukotun, R. Brown, R. Lomax, T. Mudge, and K. Sakallah. Multilevel optimization in the design of a high-performance GaAs microcomputer. IEEE Jour. Solid-State Circuits, vol. 16, no. 5, May 1991, pp. 763-767.
T. Mudge, R. Brown, W. Birmingham, J. Dykstra, A. Kayssi, R. Lomax, O. Olukotun, and K. Sakallah. The design of a micro-supercomputer. Computer, Jan. 1991, pp. 57-64.
T. Mudge, R. Brown, W. Birmingham, J. Dykstra, A. Kayssi, R. Lomax, O. Olukotun, and K. Sakallah. The design of a GaAs micro-supercomputer. Proc. Hawaii Int. Conf. System Sciences, Jan. 1991, pp. 421-432.

1990

K. Sakallah, T. Mudge, and O. Olukotun. checkTc and minTc: Timing verification and optimal clocking of synchronous digital circuits. Proc. of IEEE Int. Conf. Computer-Aided Design, Nov. 1990, pp. 552-555.
K. Sakallah, T. Mudge, and O. Olukotun. Optimal clocking of synchronous systems. TAU 90: 1990 ACM Int. Workshop Timing Issues in the Specification and Synthesis of Digital Systems, Aug. 1990, (no proceedings; appears as a tech. rept.).
O. Olukotun and T. Mudge. Hierarchical gate array routing on a hypercube multiprocessor. Jour. of Parallel and Distributed Computing, 1990, pp. 313324.
K. Sakallah, T. Mudge, and O. Olukotun. Analysis and design of latch-controlled synchronous digital circuits. Proc. of the 27-th ACM/IEEE Design Automation Conf., June 1990, pp. 111117. Nominated for best paper.
R. Clapp, T. Mudge, and J. Smith. Performance of parallel loops using alternative cache consistency protocols on a non-bus multiprocessor. Cache and Interconnect Architectures in Multiprocessors, Ed. M. Dubois and S. Thakkar, Kluwer Academic Publ., 1990, pp. 131152.
R. Clapp and T. Mudge. ADA performance issues. Ada Letters, vol. X, no. 3, Winter 1990, Chapters 1, 2, 3, 4, 5, and 8. [pdf for chapter 3]
R. Clapp, T. Mudge, and D. Winsor. Cache coherence requirements for interprocess rendezvous. Int. Jour. of Parallel Programming, vol. 9, no. 1, Jan. 1990, pp. 3151.

1989

J. Hayes and T. Mudge. Hypercube supercomputers. Proc. of the IEEE, vol. 77, no. 12, Dec. 1989, pp. 18291841.
G. Buzzard and T. Mudge. Short-latency routing for hypercube multiprocessors. Proc. 4th Conf. Hypercubes, Concurrent Computers & Applications, vol. I, Mar. 1989, pp. 285291.
R. Clapp and T. Mudge. A parallel language for a hypercube multiprocessor. Proc. 4th Conf. Hypercubes, Concurrent Computers & Applications, vol. I, Mar. 1989, pp. 515522.
P. Gottschalk, J. Turney, and T. Mudge. Efficient recognition of partially visible objects using a logarithmic complexity matching technique. The Int. Journal of Robotics Research, vol. 8, no. 6, Dec. 1989, pp. 110130.
R. Clapp and T. Mudge. Ada on a hypercube. Ada Letters, Mar.- Apr. 1989, pp. 118 128.
R. Volz, T. Mudge, G. Buzzard, and P. Krishnan. Translation and execution of distributed Ada programs: Is it still Ada? IEEE Trans. Software Engineering, vol. 15, no. 3, Mar. 1989, pp. 281292.

1988

R. Volz, T. Mudge, and A. Naylor. Wanted: A new generation of software manufacturing. Standards and Information Technology and Industrial Control, Eds. N. Malagardis and T. Williams, North-Holland, Amsterdam 1988, pp. 153168.
P. Gottschalk and T. Mudge. Efficient encoding of local shape: Features for 3-d object recognition. Proc. of the 1988 SPIE Cambridge Symp. Optical and Optoelectronic Engineering Intelligent Robots and Computer Vision: Seventh in a Series, SPIE, Cambridge MA, Nov.1988.
R. Clapp and T. Mudge. Ada on a hypercube. Proc. 3rd Int. Conf. Hypercube Concurrent Computers & Applications, Jan. 1988, pp. 399408.
G. Buzzard and T. Mudge. High performance hypercube communications. Proc. 3rd Int. Conf. Hypercube Concurrent Computers & Applications, Jan. 1988, pp. 600609.
T. Abdelrahman and T. Mudge. Parallel branch and bound algorithms. Proc. 3rd Int. Conf. Hypercube Concurrent Computers & Applications, Jan. 1988, pp. 14921499.
D. Winsor and T. Mudge. Analysis of bus hierarchies for multiprocessor. Proc. of the 15th Ann. Int. Symp. Computer Architecture, May 1988, pp. 100107.

1987

T. Abdel-Rahman and T. Mudge. Parallel branch-and-bound algorithms on hypercube multiprocessors. (Abstract) 3rd SIAM Conf. Parallel Processing for Scientific Computing, Dec. 1987.
T. Mudge. Units of distribution for distributed Ada. Proc. of the Int. W¹shop Real-Time Ada Issues, Ada UK and SIGAda, Devon, England, May 1987, also appears in Ada Letters, vol. VII, no. 6, Fall 1987. pp. 6466.
W. Martin, T. Wan, T. Abdel-Rahman, and T. Mudge. Monte Carlo photon transport on shared memory and distributed memory parallel processors. The Int. Journal of Supercomputer Applications, vol. 1, no. 3, Fall 1987, pp. 5774.
T. Mudge, H. Al-Sadoun, and B. Makrucki. A memory interference model for multi-processors based on semi-Markov processes. Institution of Electrical Engineers Proc. E, Computers and Digital Techniques, vol. 134, Part E, no. 4, July 1987, pp.203-214.
D. Winsor and T. Mudge. Crosspoint cache architectures. Proc. of the 1987 Int. Conf. Parallel Processing, Aug. 1987, pp. 266-269. [pdf file]
T. Mudge, J. Hayes, and D. Winsor. Multiple bus architectures. Computer, June 1987, pp. 42-48.
R. Volz and T. Mudge. Instruction level mechanisms for accurate real-time task scheduling. IEEE Trans. Computers, vol. C-36, no. 8, Aug. 1987, pp. 988-993.
T. Mudge. An Analysis of hypercube architectures for image pattern recognition algorithms. Proc. of the Society of Photo-optical Instrumentation Engineers Optoelectronics and Laser Applications in Science and Engineering, Image Pattern Recognition Algorithm Implementations, Techniques, and Technology: Critical Review of Technology, SPIE vol. 755, Los Angeles CA, Jan. 1987, pp. 71-83.
P. Gottschalk, J. Turney, and T. Mudge. Two-dimensional partially visible object recognition using efficient multidimensional range queries. Proc. of the 1987 Int. Conf. Robotics and Automation, Apr. 1987, pp. 380-386.
J. Han, R. Volz, and T. Mudge. Range image segmentation and surface parameter extraction for 3-D object recognition of industrial parts. Proc. of the 1987 Int. Conf. Robotics and Automation, Apr. 1987, pp. 1582-1589.
J. Hayes, R. Jain, W. Martin, T. Mudge, L. Scott, K. Shin, and Q. Stout. Hypercube computer research at The University of Michigan. Hypercube Multiprocessors 1987, Ed: M. Heath, Society for Industrial and Applied Mathematics, (Proc. of the 1986 Conf. Hypercube Multiprocessors), pp. 382-394.
T. Mudge, G. Buzzard, and T. Abdel-Rahman. A high performance operating system for the NCUBE. Hypercube Multiprocessors 1987. Ed: M. Heath, Society for Industrial and Applied Mathematics, (Proc. of the 1986 Conf. Hypercube Multiprocessors), pp. 90-99.
W. Martin, T-C. Wan, D. Poland, T. Mudge, and T. Abdel-Rahman. Monte Carlo photon transport on the NCUBE. Hypercube Multiprocessors 1987, Ed: M. Heath, Society for Industrial and Applied Mathematics, Proc. of the 1986 Conf. Hypercube Multiprocessors, pp. 454-463.
O. Olukotun and T. Mudge. A preliminary investigation into parallel routing on a hypercube computer. Proc. of the 24-th Design Automation Conf., Miami Beach, FL, June 1987, pp. 814-820.
R. Volz and T. Mudge. Timing issues in the distributed execution of Ada programs. IEEE Trans. Computers, vol. C-36, no. 4, Apr. 1987, pp. 449-459.
T. Mudge and T. Abdel-Rahman. Architectures for robot vision. in Specialized Computer Architectures for Robotics and Automation, Ed: J. Graham, Gordon and Breach Science Publ., 1987, pp. 103-149.
T. Mudge, J. Turney, and R. Volz. Automatic generation of salient features for the recognition of partially occluded parts. Robotica, vol. 5, 1987, pp. 117-127.
T. Mudge and T. Abdel-Rahman. Vision algorithms for hypercube machines. Jour. of Parallel and Distributed Computing, 79-94 (1987).

1986 and earlier

R. Clapp, T. Mudge, and R. Volz. Solutions to the n queens problem using tasking in Ada. SIGPLAN Notices, vol. 21, no. 12, Dec. 1986, pp. 99-110.
R. Volz and T. Mudge. Instruction level mechanisms for accurate real-time task scheduling. Proc. of the 1986 Real-time Systems Symp., Dec. 1986, pp. 209-215.
R. Volz, T. Mudge, G. Buzzard, and P. Krishnan. Translation and execution of distributed Ada programs: Is it still Ada? Proc. of the Society of Photo-optical Instrumentation Engineers Cambridge Symp. Advances in Intelligent Robotics Systems, SPIE vol. 727, Cambridge MA, Oct. 1986.
T. Mudge, J. Hayes, G. Buzzard and D. Winsor. Analysis of multiple-bus interconnection networks. Journal of Parallel and Distributed Computing, 328-343 (1986).
J. Hayes, T. Mudge, Q. Stout, S. Colley, and J. Palmer. A microprocessor-based hypercube supercomputer. IEEE MICRO, Oct. 1986, pp. 6-17. Best IEEE MICRO article of 1986. Also to appear in, Multi-Microprocessors, Ed. A. Gupta, IEEE Computer Society Press, 1987, pp. 250-260.
J. Hayes, T. Mudge, Q. Stout, S. Colley, and J. Palmer. Architectures of a hypercube supercomputer. Proc. of the 1986 Int. Conf. Parallel Processing, Aug. 1986, pp. 653-660.
R. Clapp, L. Duchesneau, R. Volz, T. Mudge, and T. Schultze. Toward real-time performance benchmarks for Ada. Comm. of the ACM, vol. 29, no. 8, Aug. 1986, pp. 760-778.
J. Turney, T. Mudge and R. Volz. Solving the bin of parts problem. Proc. of Vision '86, a Machine Vision Association of the SME Conf. and Exposition, Detroit, MI, June 1986, pp. 4-21 thru 4-38.
T. Mudge. The next generation of hypercube computers. Proc. of the ARO Workshop Future Directions in Computer Architecture and Software, May 1986, pp. 273-275.
R. Volz, T. Mudge, A. Naylor, and B. Brosgol. Ada in a manufacturing environment. Proc. of the Control Engineering Conf. and Exposition, Rosemont, IL, May 1986, pp. 433-440.
C. Antonelli, R. Volz and T. Mudge. Hierarchical decomposition and simulation of manufacturing cells using Ada. Simulation, 46:4, Apr. 1986, pp. 141-152.
R. Dolezal, T. Mudge, J. Turney, and R. Volz. Determining the pose of an object. Proc. of the Society of Photo-optical Instrumentation Engineers 2nd Int. Symp. Completed Vision for Robotics, SPIE vol. 595, Cannes, France, Dec. 1985, pp. 68-71.
T. Mudge. Vision algorithms for hypercube machines. Proc. of the IEEE Workshop Computer Architecture for Pattern Analysis and Image Database Management, Nov., 1985, pp. 225-230.
T. Mudge and Humoud B. Al-Sadoun. A semi-Markov model for the performance of multiple-bus systems. IEEE Trans. Computers, vol. C-34, no. 10, Oct. 1985, pp. 934-942. [pdf of scan]
J. Turney, T. Mudge, and R. Volz. Recognizing partially occluded parts. IEEE Trans. Pattern Analysis and Machine Intelligence, vol. PAMI-7, no. 4, July 1985, pp. 410-421.
T. Mudge and Humoud B. Al-Sadoun. A semi-Markov model for the performance of multiple-bus systems. Proc. of the 1985 Int. Conf. Parallel Processing, Aug. 1985, pp. 521- 530.
Humoud B. Al-Sadoun, O. Olukotun, and T. Mudge. Interconnecting off-the-shelf microprocessors. Proc. of the National Computer Conf., (AFIPS Conf. Proc. Vol. 54), July 1985, pp. 175-181.
R. Volz, T. Mudge, A. Naylor and J. Mayer. Some problems in distributing real-time Ada programs across machines. Ada in use, Proc. of the 1985 Int. Ada Conf., Eds. J. Barnes and G. Fischer, May 1985, pp. 72-84.
J. Turney, T. Mudge, and R. Volz. Recognizing partially hidden objects. Proc. of the IEEE Int. Conf. Robotics and Automation, Mar. 1985, pp. 48-54.
G. Buzzard and T. Mudge. Object-based computing and the Ada programming language. Computer, Mar. 1985, pp. 11-19. Also in: Object Oriented Computing, Ed. G. Peterson, IEEE Computer Society Press 1987, pp. 115-123.
R. Volz, T. Mudge, and J. Mayer. Some problems in distributing real time Ada programs across machines. (Abstract) IEEE Computer Society Technical Committee Real-Time Systems Newsletter, Feb. 1985. (Presented at the IEEE Second Workshop Real-Time Operating Systems Nov. 1984).
P. Leonard and T. Mudge. System design for local neighborhood processing. Proc. of the Society of Photo-optical Instrumentation Engineers Los Angeles Symp. Algorithms for Image Processing, Jan. 1985.
T. Mudge and J. Turney. Unifying robot arm control. IEEE Trans. Industry Applications, vol. IA-20, no. 6, Nov./Dec. 1984, pp. 1554-1563.
R. Volz, T. Mudge, and D. Gal. Using Ada as a programming language for robot-based manufacturing cells. IEEE Trans. Systems, Man and Cybernetics, vol. SMC-14, no. 6, Nov./Dec. 1984, pp. 863-878. Also in: Object Oriented Computing, Ed. G. Peterson, IEEE Computer Society Press 1987, pp. 99-114. Also in: Control and Programming in Advanced Manufacturing, Ed. K. Rathmill, IFS Ltd. (Springer-Verlag), 1988: Bedford, UK.
J. Turney, T. Mudge, and R. Volz. Recognizing partially hidden objects. Proc. of the Society of Photo-optical Instrumentation Engineers Cambridge Symp. Intelligent Robots and Computer Vision, Nov. 1984, pp. 108-113.
C. Antonelli, R. Volz, and T. Mudge. Hierarchical decomposition and simulation of manufacturing cells. Proc. of the 1984 Winter Simulation Conf., Nov. 1984, pp. 415-423.
T. Mudge and Humoud B. Al-Sadoun. Memory interference models with variable interconnection time. IEEE Trans. Computers, vol. C-33, no. 11, Nov. 1984, pp. 1033-1038.
R. Volz, T. Mudge, A. Woo, J. Turney, and D. Gal. CAD, robot programming and Ada. Robotics and Artificial Intelligence, Ed M. Brady, L. Gerhardt and H. Davidson, NATO Advanced Studies Institute Series, Series F: Computer and System Sciences, vol. 11, Berlin: Springer-Verlag, 1984, pp. 229-246.
R. Rutenbar, T. Mudge and D. Atkins. A class of cellular architectures to support physical design automation. IEEE Trans. CAD of IC's and Systems, vol. CAD-3, no. 4, Oct. 1984, pp. 264-278.
T. Mudge, J. Hayes, G. Buzzard, and D. Winsor. Analysis of multiple-bus interconnection networks. Proc. of the 1984 Conf. Parallel Processing, Aug. 1984, pp. 228-235. Also in: Advanced Computer Architecture, Ed. D. Agrawal, IEEE Computer Society Press 1986, pp. 155-159.
R. Volz and T. Mudge. Robots are (nothing more than) abstract data types. Proc. of the SME Conf. Robotics Research: The Next 5 Years and Beyond, (The First World Conf. Robotics Research), Aug. 1984, MS84-493, 15 pp.
T. Mudge, J. Turney, and R. Volz. Experiments in occluded parts recognition. Proc. of the Society of Photo-optical Instrumentation Engineers Cambridge Symp. Intelligent Robots, SPIE vol. 449 (part 2), Nov. 1983, pp. 719-725.
T. Mudge and T. Abdel