A
Comparison of Two Architectural Power Models
Soraya Ghiasi and Dirk Grunwald
Activity
Sensitive Microarchitectural Power Analysis
Paul E. Landman and Jan M. Rabaey
An
Instruction Level Functionality Based Energy Estimation Model
C. Brandolese, W. Fornaciari, F. Salice,
and D. Sciuto
Architectural
Level Hierarchical Power Estimation of Control Units
Rita Yu Chen, Mary Jane Irwin, and Raminder
S. Bajwa
Architectural
Power Analysis The Dual Bit Type Method
Paul E. Landman and Jan M. Rabaey
High
Level Area and Power Estimation for VLSI Circuits
Mahadevamurty Nemani and Farid N. Najm
High
Level Power Estimation
Paul Landman
Microarchitectural
Power Analysis for CPU Power Performance Optimization
George Z. N. Cai and Chee How Lim
Power
Estimation for Architectural Exploration of HW/SW Communication on System
Level Buses
William Fornaciari, Donatella Sciuto,
and Cristina Silvano
Validation
of an Architectural Level Power Analysis Technique
Rita Yu Chen, Robert M. Owens, Mary Jane
Irwin, and Raminder S. Bajwa