- Assistant:
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Lauri Johnson
CSE #4808 - ACAL Lab
lkjohns@eecs.umich.edu
734 763.4921 - Teaching this semester
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Fall 2010:
EECS 370 - Introduction to Computer Architecture
- Recent publications
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"Fault-Based Attack of RSA Authentication"
Andrea Pellegrini, Valeria Bertacco and Todd Austin
Design Automation and Test in Europe, Dresden, Germany, March 2010 -
"Event-Driven Gate-Level Simualation with GP-GPUs"
Debapriya Chatterjee, Andrew DeOrio and Valeria Bertacco
Design Automation Conference, San Francisco, CA, July 2009 -
"Vicis: A Reliable Network for Unreliable Silicon"
David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, Dennis Sylvester and David Blaauw
Design Automation Conference, San Francisco, CA, July 2009 -
"DACOTA: Post-silicon Validation of the Memory Subsystem in Multi-Core Designs"
Andrew DeOrio, Ilya Wagner and Valeria Bertacco
International Symposium on High-Performance Computer Architecture (HPCA), Raleigh, NC, February 2009
Research interests
I am interested in the functional correctness of hardware designs, focusing in the creation of novel techniques to guarantee correctness in face of functional errors and temporary and permanent transistor failures.
My present research and my professional experience are centered on the development of new algorithms for hybrid verification and post-silicon validation and debug. This focus is extended to support the correctness of designs after completion and in the field, through techniques that use dynamic verification and novel reliability mechanisms to extend the lifetime of an IC design and to provide guarantees on its correct behavior, in face of the challenges posed by fragile silicon and extreme design complexity.
FunSAT
Current release: FunSAT 1.1
Affiliation
I am part of the Advanced Computer Architecture Lab in the EECS Department of the University of Michigan. The lab includes 14 faculty members and approximately 65 students. The Lab is part of the Computer Science and Engineering division.
Short biography
Valeria Bertacco is an Associate Professor of Electrical Engineering and Computer Science at the University of Michigan. Her research interests are in the area of design correctness, with emphasis on full design validation, digital system reliability and hardware security assurance. Valeria joined the faculty at Michigan after being in the Advanced Technology Group of Synopsys for four years as a lead developer of Vera and Magellan, two popular verification tools.
Valeria serves in several conference program committees, including DATE and DAC, she is an Associated Editor for the IEEE Transactions on CAD and the Microelectronics Journal, and the author of two books on design errors and validation. She received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1998 and 2003, respectively; and a Computer Engineering degree ("Dottore in Ingegneria") summa cum laude from the University of Padova, Italy in 1995. Valeria is the recipient of an NSF CAREER award, a University of Michigan's Outstanding Achievement award and the Air Force Office of Scientific Research's Young Investigator award.