Assistant:
Lauri Johnson
CSE #4812 - ACAL Lab
lkjohns@eecs.umich.edu
734 763.4921

Teaching this semester
Winter 2009:
EECS 270
- Introduction to Logic Design

Recent publications
"DACOTA: Post-silicon Validation of the Memory Subsystem in Multi-Core Designs"
Andrew DeOrio, Ilya Wagner and Valeria Bertacco
International Symposium on High-Performance Computer Architecture (HPCA), Raleigh, NC, February 2009

"Reversi: Post-Silicon Validation System for Modern Microprocessors"
Ilya Wagner and Valeria Bertacco
IEEE International Conference on Computer Design (ICCD), Lake Tahoe, CA, October 2008
- Best Paper Award

"Testudo: Heavyweight Security Analysis via Statistical Sampling"
Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd Austin, Valeria Bertacco and Seth Pettie
International Symposium on Microarchitecture (MICRO), Lake Como, Italy, November 2008

"CrashTest: A fast High-Fidelity FPGA-based Resiliency Analysis Framework"
Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco and Todd Austin
IEEE International Conference on Computer Design (ICCD), Lake Tahoe, CA, October 2008

Research interests

I am interested in the functional verification of hardware designs, focusing mainly in the creation of novel techniques and verification methodologies that enable the formal and semi-formal verification of industrial scale designs.
My present research and my professional experience are centered on the development of new algorithms for hybrid, semi-formal verification which lead to a high level of confidence in the correctness of a design, while minimizing demands on the verification team.
This focus is extended to guaranteeing the correctness of designs after completion and in the field, through techniques that use dynamic verification and novel reliability mechanisms to extend the lifetime of an IC design, in face of the challenges posed by fragile silicon and extreme design complexity.

FunSAT

Current release: FunSAT 1.0

Affiliation

I am part of the Advanced Computer Architecture Lab in the EECS Department of the University of Michigan. The lab includes 12 faculty members and approximately 65 students. The Lab is part of the Computer Science and Engineering division.

Short biography

Valeria Bertacco is an Associate Professor of Electrical Engineering and Computer Science (effective 9/1/09) at the University of Michigan. Her research interests are in the area of design verification, with emphasis on full design validation, digital system reliability and hardware security assurance. Valeria joined the faculty at Michigan after being in the Advanced Technology Group of Synopsys for four years as a lead developer of Vera and Magellan, two popular verification tools. Valeria serves in several conference program committees, including DATE, DAC and ICCAD, she is an Associated Editor for the IEEE Transactions on CAD and the author of two books on design errors and validation. She received her M.S. and a Ph.D. degree in Electrical Engineering from Stanford University in 1998 and 2003, respectively and a computer engineering degree ("Dottore in Ingegneria") summa cum laude from the University of Padova, Italy in 1995. Valeria is the recipient of an NSF CAREER award, a University of Michigan's Outstanding Achievement award and the Air Force Office of Scientific Research's Young Investigator award.