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EECS 578
Computer-Aided Design Verification of
Digital Systems
Fall 2009
Prof. Valeria Bertacco
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photo by Alex Fasan
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NEWS - NEWS - NEWS
- 11/20 - Practice midterm exams posted
General Information
Paper Presentations
Term Project
Course Projects
- Runtime Verification of Interconnect Routers in Networks on Chips
Authors: Rawan Abdel Khalek and Davoud Anoushe Jamshidi
Outline
Checkpoint 1
- CASPAR Deployment in a Multi-Core Envinronment
Authors: Zohair Ahmad
Outline
Checkpoint 1
- Comparing Vera's Constraint-based Input Stimulus Generation to SAT
Authors: Mike Pavlak
Outline
Checkpoint 1
- Equivalence Checking of SystemC and RTL Designs
Authors: BK Kim and Jay Chung
Outline
Checkpoint 1
- Using Verification to Define Architecture for Video-based IPs
Authors: Paritosh Gupta
Outline
Checkpoint 1
- Compact Signature Generation for Use in Verification Applications
Authors: Anthony Gutierrez, Daya Khudia and Bobby Li
Outline
Checkpoint 1
- Symbolic Simulation
Authors: Ritesh Parikh and Ankit Sethia
Outline
Checkpoint 1
- Design of Fault-Tolerant Digital Microfluidics-based Biochips
Authors: Yu-Chih Chen, Win San Khwa and Ming Han Victor Yu
Outline
Checkpoint 1
- FRCL-based Runtime Verification of Inner Cores for Networks
Authors: Bhavitaviya Bhadviya and Anu Chaudhary
Outline
Checkpoint 1
Mini-projects
Mini-projects can be developed by consulting or working
together with classmates. However, each student should submit
his/her own individual and original source code and project write-up.
Projects should be submitted by midnight on the day they are due by
emailing valeria@umich.edu. The class forum can be used to post questions
and ask for clarifications.
- Vera project - due 09/18/09
- SAT project - due 09/25/09
- Magellan project - due 10/02/09