`timescale 1ns/1ns
module lab5tb();
reg C0_s, C1_s;
reg[3:0] A_s, B_s;
wire [4:0] S_s;
integer i;
//the connection from the test cases to the calculator assumes the A, B and S
//connections are buses greatly simplifying the port connections
my_calc t1(.C0(C0_s), .C1(C1_s), .A(A_s), .B(B_s), .S(S_s));
initial begin
/* create test cases for 5 + <-8 to 7> */
A_s = 5;
B_s = 0;
C0_s = 0; C1_s = 0;
//the FOR loop can be used to create all the test cases from -8 o 7. Notice that
//this is accomplished by simply incrementing i from 0 to 16 since the numbers
//are interpreted by the calculator as 2's complement numbers.
for(i = 0; i <= 16; i = i+1)
begin
#10;
B_s = i;
end
end
endmodule