This is an individual assignment, all of the work should be your own. Assignments that are unstapled, lack a cover sheet, or are difficult to read will lose at least 50% of the possible points and we may not grade them at all.

This assignment is worth about 1% of your grade in the class and is graded out of 30 points. Remember you may drop one individual homework assignment.

1. Find the minimal product-of-sums for each of the following [4]
   1. F=Π_(w,x,y,z)=(0,2,8,9,10)+d(1,3)
   2. F=abc+!(ab)+!(!a!b)
2. Design a 4 to 1 MUX using only tri-state devices and inverters. [4]
3. Assuming NOT gates have a delay of 1ns, NOR/NAND gates have a delay of 3ns, AND/OR gates have a delay of 4ns and XOR/XNORs have a delay of 7ns, what would be the worst-case delay associated with the 4-bit ripple-cary adder shown in figure 4.31? Assume the parts are built as shown in figures 4.28 and 4.30 . [5]
4. As the problem above but for figure 6.56 (b) and (c). [7]
5. Consider the following state table. Minimize the number of states. Give your answer as a state table. [5]

   State   Next State   Output (W)
            X=0  X=1      
     A       B    A       0
     B       C    G       0
     C       E    C       0
     D       B    A       1
     E       F    G       0
     F       B    F       0
     G       A    D       1
   

6. Given a 1024 by 1024 RAM block, answer the following questions [5]
   1. If we used that to make an 8-bit wide memory
      1. How many locations would there be?
      2. How many address bits would we need to address those locations?
      3. How many of those address bits would go to the decoder? The MUX?
   2. If we used that to make a 4-bit wide memory
      1. How many locations would there be?
      2. How many address bits would we need to address those locations?
      3. How many of those address bits would go to the decoder? The MUX?