This assignment is worth about 1% of your grade in the class and is graded out of 30 points. Remember you may drop one individual homework assignment.

1. 3.13 [1]
2. 3.15 [1]
3. 3.40 but you don't need to draw the gates, "just" write the logic equations for each combinational output in the box where you'd put the gates. Show your work. Use 00 for A, 01 for B, 10 for C and 11 for D. [7]
4. 3.48 --Draw the FSM. [4]
5. Convert the following FSM to a controller. There is one output, "bob" which should be a 1 iff you are in state "Y". Show your work. (To make the grader's life easier, let's all use the same state encoding: 00 for Y, 01 for X and 10 for Z).

   Other than your work, all we want is that you provide the logic equations for D₁, D₀ and Bob. [7]

   

6. Consider the circuit found in figure 3.113. Assume that all bubbles are inverters. Assume that the input always appears 15ps after the rising edge of the clock. The various parts have the following characteristics:
   • State register: Clock to Q: 20-50ps, hold time 45ps, setup time: 50ps
   • Inverter: delay 5-20ps
   • 2-input gate: delay 10-30ps
   • 3-input gate: delay 15-45ps
   1. Is there a potential hold time violation with the state register? If so, redraw the circuit adding inverter pairs as needed to address the problem. Add as few pairs as possible. If there is more than one way to do that, do so in a way that minimizes the impact on the clock period (part b). Clearly show your work to receive credit. [4]
   2. After having added the needed inverter pairs, what is the fastest clock frequency at which you can clock this circuit. Again, clearly show your work to receive credit.[6]