EECS 270


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Lectures are all remote. Zoom link is with a passcode of EECS270.

Office hours are also remote. See the "staff" page for Zoom links.

Lab is hybrid. You may come to lab or do it remotely. Lab periods will generally consist of the lab instructor providing a brief overview of the lab. That presentation will be available in person, but also on Zoom at To enter the help queue, if in-person or remote, go to If you are remote, you must provide a Zoom or other meeting link when you sign up. If you are local, you must indicate which room you are in and which computer you are using..

Remote lab
You are to attend your lab section. If you are in the purely remote section, you will be contacted individually with further directions. You are to watch the lab instructor's introduction each week via Zoom (link above). These will often be quite short, so get there on time. You will be using two different tools. You will want to get the VNC set up before your first lab. More directions will be provided in lab and on the webpage.
Everyone who is coming to lab in person will receive a face shield. You will only get one and you will need to take it to and from lab. If you lose it, you'll need to purchase one. When interacting closely with the lab instructor, both you and the lab instructor will need to wear a face shield while you are within 6 feet of each other. Because of Covid occupancy restrictions, we can only have 9 students in the primary lab. EECS 2331 is our "overflow" room. It is normally a CAEN lab. If the main lab room (2322) is full, you'll need to go to the overflow room. Once you have a lab station, you need to wipe down the station (FPGA board, the keyboard, the the table immediately in front of you). When you leave the lab and are done using the station, you need to wipe it all down again.

You will need to wear a mask in the lab at all times. No food or drink is allowed. You need to maintain spacing between yourself and others in the lab (6 feet) and should stay in your seat unless entering or exiting the lab. When the lab instructor comes to help you, you will need to put on your face shield.

You are to read the complete operating procedure for the lab before the first time you enter.


Digital design, with RTL design, VHDL, and Verilog (second edition) by Frank Vahid

The book is stupidly expensive, but you really do need it. If push comes to shove, the first edition of the book is better than nothing, but you'll really want the second edition if possible. Note that the midterms and final are (mostly or entirely) open book and open notes.

Course Goals

This course is intended to give you an understanding of digital logic. We will mostly concern ourselves with gate-level designs, but we will also address one level of abstraction up (larger logic devices such as MUXes, adders, counters etc.) and one level down (CMOS logic). There will be a heavy emphasis on learning design tools in your lab sections, and, in the latter half of the course, the use of a hardware description language (HDL), namely the Verilog HDL, to complete labs.

Class Labs

Lab due dates/times, as well as the lab documents can be found here. For each day an in-lab assignment is late, you will be penalized by 20% of the total points earned (so after 5 days you get no points). Details about the expectations for the lab write-ups will be communicated as those labs are assigned. Notice that failure to do the labs will have a serious impact on your grade.

Homework assignments

You will be assigned about 11 homework assignments (7 individual, 4 group is the plan).

Your homework score will be computed by dropping your lowest individual and group homework grades. This policy exists to address issues such as illness, poor internet connects, hungry dogs/cats, useless partners (for group assignments) etc. In the event of exceptional circumstances on more than that, please see the instructor. Homework (including group assignments) will generally be due on Tuesdays at 9pm via Gradescope.

Group Assignments: Student groups will consist of no more than three students, though they can be done in groups of 2 or even individually. These assignments will generally be difficult and have a design component. You should schedule about 3 hours together to do these assignments. Groups can freely change for each assignment (though we don't recommend it) and having non-contributing members listed on an assignment is an honor code violation. In the past we've see that there is a tempation to break the assignment up so that one person does one assignment, another does the next, etc. That is a really bad idea. You won't learn the material you need for the exams and it's also really likely your grade on the assignment will be much lower than it would be if you all worked together. These assigments are designed to be much easier with a group bouncing around ideas. The are also generally fairly rough.

Doing your own labs and homework

All labs and individual homeworks are to be done on your own. Violation of this policy will result in the inititiation of formal procedures the Engineering Honor Council. Group assignments are to be done only by members of that group.

At the same time, we encourage students to help each other learn the course material. As in most courses there is a boundary separating these two situations. In general, you can discuss concepts of the course or the specifics of the lab software. But you may not collaborate in any way when constructing a solution. If you have any questions about what constitutes unacceptable collaboration, please talk to the instructor.


There will be two midterms and a final.

The midterms and final will be open book, open note, and probably open-internet and you may use a calculator. There may be parts that are closed book and if so we'll hard hard to make it clear what you need to be able to do without notes or a book.


Furthermore, for each in-lab assignment in which you do not complete, you will have your course grade lowered by 1/3 a letter grade (B to B-, for example.) The class median will likely be a "B-", the average around 2.9.

Regrade Policy

If you feel that you were graded unfairly on a homework assignment, lab, or exam, you have exactly one week from when the assignment is handed back to request a regrade. These regrade requests should be clearly written.

Regrade requests for exams and homework will be generally handled via gradescope. Lab regrades will be addressed by your lab instructor. You can appeal a regrade request to Dr. Brehob in his office hours (though again, you must do so within a week of when the regrade request was responded to). We reserve the right to regrade the entire assignment when a regrade request is made.

Home / announcements | Course overview | Staff and hours | References / Handouts
Piazza | Gradescope | Schedule | Homework | Labs