EECS 470: Computer Architecture

Homework

Homework is generally due at 10 pm on the due date.

• Homework 1 (answers)
• Homework 2. (answers)
• Homework 3. (answers)
• Homework 4. (answers)
• Homework 5.

Verilog

Helpful Verilog Guidelines

In lab

Lab assignment sign off sheet

• Lab 1
  • Slides from Lab
  • Lab Assignment
• Lab 2
  • Slides from Lab
  • Lab Assignment
• Lab 3
  • Slides from Lab
  • Lab Assignment
• Lab 4
  • Slides from Lab
  • Lab Assignment
• Lab 5
  • Slides from Lab
  • Lab Assignment
• Lab 6
  • Slides from Lab
• Lab 7
  • Slides from Lab

Verilog Programming Assignments

• Project 1
• Project 2
• Project 3
  • P3 RISC-V Intro Slides

Final Project

• Project handout
• Project report (written and oral) guidelines

Some Sample Verilog Modules...

• sample_rs.v
• wor_example.v