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EECS 478: Logic Circuit Synthesis and Optimization

Instructors: Igor Markov
                    --John Hayes
                  --  Valeria Bertacco

Advanced concepts in digital logic and integrated circuits. Computer-aided design process and relevant algorithms. Theoretical foundations: two-level and multilevel optimization of combinational circuits. Verification of digital logic. Optimization of finite-state machines.

Three projects in which students develop CAD tools for circuit analysis and synthesis. C++ programming is required. Being familiar with algorithms and data structures (EECS 281) is recommended.

Hachtel, Gary D., and Fabio Somenzi. Logic Synthesis and Verification Algorithms. 1st ed. Boston, MA.: Springer, 2006.

1. Digital logic and integrated circuits.
2. Design process and technology styles.
3. Prerequisites review: Combinational and sequential circuit design.
4. Datapath circuit design and optimization using polynomial algebra.
5. Basic theory: set and graph concepts.
6. Timing analysis and functional simulation.
7. Formal verification
8. Boolean algebras. Relations. Lattices. Algebra of Boolean functions.
9. Cofactors. Boole/Shannon theorem. Binary decision diagrams (BDDs).
10. Two-level optimization. Cube representation. Unate functions.
11. Multilevel optimization. Algebraic division methods.
12. Finite-state machines and sequential circuit optimization.
13. Contemporary topics in digital logic.