ECE
ECE
ECE ECE


MICL Seminar

Accelerating Data Analysis for Next-Generation Sequencing

Chia-Hsiang Yang


Professor
National Taiwan University
 
Wednesday, May 15, 2019
10:30am - 11:30am
1012 EECS

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About the Event

DNA sequencing is the process of determining the precise order of nitrogenous bases within a DNA molecule. It is now an indispensable tool for determining the cause of genetic diseases and for developing associated treatments. Next-generation sequencing (NGS) is currently the fastest sequencing technique and can sequence the short fragments in a massively parallel fashion, achieving orders of magnitude higher throughput than the first-generation sequencing technique. However, as the throughput of NGS growth exponentially, the succeeding data processing and analysis are still excessively time consuming. In this talk, I will present an NGS data processor ASIC that realizes DNA mapping, including suffix array (SA) sorting and backward searching. An efficient hardware architecture is proposed to address the extremely time-consuming SA sorting issue. With the optimized hardware parameters, 98.4% memory and 96.7% latency reductions are achieved. The chip achieves 43,065x and 8,971x [3,208 and 402x] higher energy efficiency [throughput-to-area ratio] than the high-end CPU and GPU solutions, respectively.

Biography

Chia-Hsiang Yang received his B.S. degree in Electrical Engineering in 2002, B.B.A degree in Information Management in 2002, and M.S. degree in Electronics Engineering in 2004, from the National Taiwan University. He received his Ph.D. degree from the Department of Electrical Engineering of the University of California, Los Angeles in 2010. He then joined the faculty of the Electronics Engineering Department at the National Chiao Tung University. In 2015, he moved to the National Taiwan University, where he is currently a Full Professor. His research interests include energy-efficient integrated circuits and architectures for biomedical and communication signal processing. Dr. Yang was a winner of the DAC/ISSCC Student Design Contest in 2010. He received the 2010-2011 Distinguished Ph.D. Dissertation in Circuits & Embedded Systems Award from the Department of Electrical Engineering, University of California, Los Angeles. In 2013, he was a co-recipient of the ISSCC Distinguished-Technical-Paper Award and Demonstration Session Certification of Recognition. He is also the advisor for several student awards, including the 2017 ISSCC Silkroad Award. He served on the IEEE Asian Solid-State Circuit Conference (A-SSCC) Technical Program Committee (TPC) and was the TPC Vice-Chair for 2017 A-SSCC. He has also served as a Guest Editor of the IEEE Journal of Solid-State Circuits (JSSC) and is also serving as an Associate Editor of the IEEE Signal Processing Letters (SPL).

Additional Information

Contact: Fran Doman

Phone: 734 615-3499

Email: fdoman@umich.edu

Sponsor(s): MICL

Faculty Sponsor: Zhengya Zhang

Open to: Public