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Fall 2013: EECS 598 Ultra-Low-Power CMOS Circuit Design

Course No.: EECS 598
Credit Hours: Up to 4 credits
Instructor: Pinaki Mazumder
Prerequisites: EECS 312 or EECS 427 or permission of instructor

Course Description:
Following the trajectory of the Moores Law, the integration density of VLSI chips has grown exponentially from two thousand transistors per chip in the early Seventies (i4004) to over one billion transistors (Itanium) in 2009. During this time, CMOS VLSI design has witnessed multiple generations of evolution as the CMOS circuit design focus gradually shifted from Silicon real estate (in the late 70s) to timing closure (in the late 80s), to power aware (in the late 90s), and then to process variations(reliability) at sub-100 nm transistor dimensions. This course envisages studying energy-aware CMOS circuit design techniques that are currently being used in building low-power (at nominal supply voltage) and ultra-low-power (in subthreshold region) VLSI systems. Students interested in taking this course must have basic background in CMOS design (equivalent to EECS 312) and are expected to know circuitequations for minimization of power consumption as well as energy-delay optimization. The course will mainly focus on various aspects of sub-threshold CMOS circuit design as outlined below.
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