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CSE Technical Reports Sorted by Technical Report Number


TR Number Title Authors Date Pages
CSE-TR-193-94 Instructable Autonomous Agents Huffman Jan, 94 142
CSE-TR-194-94 Scheduling for Modern Disk Drives and Non-Random Workloads Worthington Ganger and Patt Mar, 94 45
CSE-TR-195-94 Effect of Fan-Out on the Performance of a Single-Message Cancellation Scheme Prakash Wu and Jetli Feb, 94 11
CSE-TR-196-94 Undoing Actions in Collaborative Work: Framework and Experience Prakash and Knister Mar, 94 26
CSE-TR-197-94 Architectural Support for Managing Communication in Point-to-Point Distributed Systems Feng Rexford Mehra Daniel Dolter and Shin Mar, 94 16
CSE-TR-198-94 Optimal Local Register Allocation for a Multiple-Issue Machine Meleis and Davidson Mar, 94 15
CSE-TR-199-94 Schema Evolution for Real-Time Object-Oriented Databases Zhou Rundensteiner and Shin Mar, 94 20
CSE-TR-200-94 Unix I/O Performance in Workstations and Mainframes Chen and Patterson Mar, 94 15
Rapid advances in processor performance have shifted the performance bottleneck to I/O systems. The relatively slow rate of improvement in I/O is due in part to a lack of quantitative performance analysis of software and hardware alternatives. Using a new self-scaling I/O benchmark, we provide such an evaluation for 11 hardware configurations using 9 variations of the Unix operating system. In contrast to processor performance comparisons, where factors of 2 are considered large, we find differences of factors of 10 to 100 in I/O systems. The principal performance culprits are the policies of different Unix operating systems; some policies on writes to the file cache will cause processors to run at magnetic disk speeds instead of at main memory speeds. These results suggest a greater emphasis be placed on I/O performance when making operating system policy decisions.
CSE-TR-201-94 Evaluation of Fault-Tolerance Latency from Real-Time Application's Perspectives Kim and Shin Mar, 94 19
CSE-TR-202-94 Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation Riepe Silva Sakallah and Brown Mar, 94 22
Ravel-XL is a single-board hardware accelerator for gate-level digital logic simulation. It uses a standard levelized-code approach to statically schedule gate evaluations. However, unlike previous approaches based on levelized-code scheduling, it is not limited to zero- or unit-delay gate models and can provide timing accuracy comparable to that obtained from event-driven methods. We review the synchronous waveform algebra that forms the basis of the Ravel-XL simulation algorithm, present an architecture for its hardware realization, and describe an implementation of this architecture as a single VLSI chip. The chip has about 900,000 transistors on a die that is approximately 1.4cm^2, requires a 256-pin package and is designed to run at 33MHz. A Ravel-XL board consisting of the processor chip and local instruction and data memory can simulate up to one billion gates at a rate of approximately 6.6 million gate evaluations per second. To better appreciate the tradeoffs made in designing Ravel-XL, we compare its capabilities to those of other commercial and research software simulators and hardware accelerators.
CSE-TR-203-94 IDtrace - A Tracing Tool for i486 Simulation Pierce and Mudge Mar, 94 25
CSE-TR-204-94 Data and Program Restructuring of Irregular Applications for Cache-Coherent Multiprocessors Tomko and Abraham Mar, 94 26
CSE-TR-205-94 Reduction of Cache Interference Misses Through Selective Bit-Permutation Mapping Abraham and Agusleo Mar, 94 26
CSE-TR-206-94 Partitioning Regular Applications for Cache-Coherent Multiprocessors Tomko and Abraham Mar, 94 25
CSE-TR-207-94 Collected Papers of the Soar/IFOR Project Laird et.al. Apr, 94 100
CSE-TR-208-94 Coordinating Decision Making in Large Organizations Birmingham D'Ambrosio Darr and Durfee Apr, 94 5
CSE-TR-209-94 Supporting Queries on Source Code: A Formal Framework Paul and Prakash Apr, 94 20
CSE-TR-210-94 An Object-Oriented Real-Time Database System for Multiprocessors Lortz Apr, 94 132
CSE-TR-211-94 A Transparent Object-Oriented Schema Change Approach Using View Evolution Ra and Rundesteiner Apr, 94 36
CSE-TR-212-94 Runtime Monitoring of Timing Constraints in Distributed Real-Time Systems Jahanian Rajkumar and Raju Apr, 94 21
CSE-TR-213-94 An Active Visual Estimator for Dexterous Manipulation Rizzi and Koditschek May, 94 32
CSE-TR-214-94 An Active OODB System For Genome Physical Map Assembly Lee Rundensteiner and Thomas May, 94 24
CSE-TR-215-94 A Flexible Object-Oriented Database Model and Implementation for Capacity-Augmenting Views Ra Kuno and Rundensteiner Apr, 94 19
CSE-TR-216-94 Automatic Acquisition of Word Meaning From Context Hastings May, 94 128
CSE-TR-217-94 Probing and Fault Injection of Protocol Implementations Dawson and Jahanian Oct, 94 21
CSE-TR-218-94 PLINK: An Intelligent Natural Language Parser Huyck Aug, 94 102
CSE-TR-219-94 The Evolution of the Soar Cognitive Architecture Laird and Rosenbloom Sep, 94 43
CSE-TR-220-94 Conceptual Modeling of Manufacturing Automation Birla Sep, 94 44
CSE-TR-221-94 An Attribute-Space Representation and Algorithm for Concurrent Engineering Darr and Birmingham Oct, 94 19
CSE-TR-222-94 Wrong-Path Instruction Prefetching Pierce and Mudge Nov, 94 16
CSE-TR-223-94 Broy-Lamport Specification Problem: An Evolving Algebras Solution (update see 320-96) Huggins Aug, 94 10
CSE-TR-224-94 Design ing Databases with Fuzzy Data and Rules for Application to Discrete Control Chaudhry Moyne and Rundensteiner Nov, 94 21
CSE-TR-225-94 A Graphical Query Language for Identifying Temporal Trends in Video Data Hibino and Rundensteiner Dec, 94 17
CSE-TR-226-94 Fault-Tolerant Interconnection Networks for Multiprocessors Ku Dec, 94 124

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