EECS 270: Course Overview

Textbook

Digital Design, Frank Vahid

Course Goals

This course is intended to give you an understanding of digital logic. We will mostly concern ourselves with gate-level designs, but we will also address one level of abstraction up (larger logic devices such as MUXes, adders, counters etc.) and one level down (CMOS logic). There will be a heavy emphasis on learning design tools in your lab sections, and, in the latter half of the course, the use of a hardware description language (HDL), namely the Verilog HDL, to complete labs.

Class Labs

Labs and prelabs are due in the first 30 minutes of your lab section unless otherwise noted. For each day an in-lab assignment is late, you will be penalized by 10% of the total points earned (so after 5 days you get no points). Details about the expectations for the lab write-ups will be communicated as those labs are assigned. Notice that failure to do the labs will have a serious impact on your grade.

Homework assignments

You will be assigned about 12 homework assignments (8 individual, 4 group) assignments and each will be graded out of 30 points.

Your homework score will be computed by dropping your two lowest homework grades. This policy exists to address issues such as illness, broken cars, late buses, hungry dogs/cats, useless partners (for group assignments) etc. In the event of exceptional circumstances on more than two assignments, please see the instructor.

Homework is due at 2pm in the class box (location will be announced in class) on the day it is due.

Group Assignments: Student groups will consist of no more than three students, though they can be done in groups of 2 or even individually. These assignments will generally be difficult and have a design component. You should schedule about 2 to 3 hours to meet to do these assignments. Groups can freely change for each assignment (though we don't recommend it) and having non-contributing members listed on an assignment is an honor code violation. In the past we've see that there is a tempation to break the assignment up so that one person does one assignment, another does the next, etc. Not only is that an honor code violation, it's also a really bad idea. You won't learn the material you need for the exams and it's also really likely your grade on the assignment will be much lower than it would be if you all worked together. These assigments are designed to be much easier with a group bouncing around ideas...

Doing your own labs and homework

All labs and individual homeworks are to be done on your own. Violation of this policy will result in the inititiation of formal procedures the Engineering Honor Council. Group assignments are to be done only by members of that group.

At the same time, we encourage students to help each other learn the course material. As in most courses there is a boundary separating these two situations. In general, you can discuss concepts of the course or the specifics of the lab software. But you may not collaborate in any way when constructing a solution. If you have any questions about what constitutes unacceptable collaboration, please talk to the instructor.

Exams

There will be two midterms and a final. Exams will be open book, open note and you may use a calculator. Computers and devices capable of comminication (which includes certain calculators!) are not allowed.

Grading

Furthermore, for each in-lab assignment in which you do not complete, you will have your course grade lowered by 1/3 a letter grade (B to B-, for example.) The class median will likely be a "B-".

Regrade Policy

If you feel that you were graded unfairly on a homework assignment, lab, or exam, you have exactly one week from when the assignment is handed back to request a regrade. These regrade requests should be writen and clear.

Homework and group assignment regrades will be handled by the instructional GSI. Exam regrades will be addressed by the instructors during their office hours. Lab regrades will be addressed by your lab instructor with the option of appealling to the lab coordinator. We reserve the right to regrade the entire assignment.