EECS 270: Introduction to Logic Design

NOTE: It is in your best interests to complete all of the lab assignments, even if your lab is so late that you will receive a grade of 0 on it. Failure to complete the in-lab portion of a lab will result in a 1/3 letter grade deduction in your overall course grade for each incomplete lab (e.g. a B will fall to a B-, D- to E, etc.).

Lab Postings and Schedule

• Lab Overview
• Quartus Tutorial
• Printing set-up in Quartus
• Lab coversheet
• assignment_defaults.qdf
• pin assignments (pdf file).
• Buses in Quartus (pdf file).
• Verilog reference material:
  • Combinational logic
  • Sequential logic -- This won't print correctly from the 270 lab, but it will from the CAEN lab. Don't know why...
• Quartus Web Download -- updated 5/4/07

NOTES:

• Due to the Memorial Day holiday on May 28, students in the Monday/Wednesday lab will have a make-up lab session on Tuesday, May 29, from 4:30-7:30.

Open lab hours

See the staff and hours page or the lab hours handout above for details.