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A Quadrature GPS Receiver Front-End in 0.13μm CMOS

Po-Chia Lai, Yee-Huan Ng, Jia Ruan

Abstract

We will be designing a stacked quadrature LNA-mixer-VCO (QLMV) cell for GPS receiver in 0.13 µm CMOS. Our design is based on a similar research in [1], [2]. The overall goal of this project is to match the power consumption of their RF front end and their noise figure of 6.5 dB. Our design will involve a stacked QLMV cell to exploit the dc bias current reuse for low power consumption. The application of double-balanced mixers and gate-modulated VCO will improve the accuracy of quadrature phase signal generation. Figure 1 shows how our QLMV cell will fit within a GPS receiver at the system level. Figure 2 shows how the cell will be implemented in the circuit level. The challenging part of this project will be combining the LNA, mixer and VCO. If time permits, we will also consider including a balun in our circuit.

1. Kuang-Wei Cheng, et al., "A Current Reuse Quadrature GPS Receiver in 0.13 µm CMOS", Solid-State Circuits, IEEE Journal of, vol.45, no.3, March 2010.
2. Kuang-Wei Cheng, et al., "A 7.2mW Quadrature GPS Receiver in 0.13 μm CMOS" IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009.

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