Note: This tutorial is for the Linux toolset. The directions likely apply to the Windows version also, but have not been tested there. In lab we expect you to use the Linux toolset.
TABLE 1: Truth Table for Majority Voter
A B C M
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Click the "Create a New Project (New Project Wizard)" at the splash screen. A screen will appear that has 3 lines of text to fill in. The first line will be populated with the path to your AFS space. For the directory select any directory name, though we recommend you use something like 270labs/tutorial. For the name of the project and the top level-design entity, use "tutorial". Your window should now look like this screenshot. Select "Next". You should be prompted if you wish to create the directory. Select "yes". You have now created a new project.
It is best to put each lab or project in it's own directory. For example, when you start lab 1 the path should be 270labs/lab1, lab 2 should be 270labs/lab2, etc.
Next you will be prompted to add design files. We will create design files a bit later, so skip this window.
Now you need to tell the software what type of device you will be using. First select Device Family to be Cyclone IVE. Under Available Devices select EP4CE115F29C7. If you look on the DE2 board, you will notice that this is the name and device of the Altera chip. The window should look like this.
Proceed thru the last to windows (4 and 5) and using the default settings.
This will launch the schematic editor. On the left side of the Schematic Editor window is a toolbar containing the different modes of the editor. To change modes, simply click on the appropriate icon. You can also use the "Esc" key to go to the default "Select and Drag" mode. For this tutorial we will be using only the following three modes:
A pop-up window titled "Symbol" will appear. Click on the "plus" sign under libraries and then on the "primitives" and finally "pin". The Symbol window should now look like this screenshot. Make sure that the "repeat-insert mode" checkbox is selected. Select "input" under pins and press OK. As our circuit has three inputs, place the three input pins on the left side of the screen. Do the same thing again, but placing one output on the right side. Your design should look similar to this screenshot. Note that you can move an existing pin by switching to the selection mode. You can also delete a pin by selecting it and then pressing the "delete" key on the keyboard. You can also return to the selection tool by pressing the "Esc" key on the keyboard.
Next, we wish to give these pins names. Right click on each pin and select "properties" OR double-click on the pin. Change the input names of each of the three inputs to A, B or C. Change the output pin's name to "M". The screen should now resemble this screenshot.
Now add three 2-input AND gates and two 2-input OR gates. You will want the AND gates in a column to the right of the input pins and the OR gates to the right of them (as seen in Figure 2, above). Don't worry about the wires yet. You can select the gates by using the Symbol tool under "primitives" then "logic". You want "and2" and "or2" (see here for selecting a 2-input AND gate). Once you've added the five gates, your design should resemble this screenshot.
This would be a good time to save your design. Select File → Save Project and respond in the affirmative to any dialog box which may come up. In general, you should save your work every five minutes or so. We've had a few problems with the tool crashing.
Next, switch to wiring mode and connect the gates and pins so as
to implement
the function shown in Figure 2. You may find that the tool doesn't
always place the wire in the way you'd like. This can be a real
problem
when the tool ends up connecting a given wire to things you hadn't
intended.
A trick is to draw the wire "part way" to where you want it and
then
end the wire. From that point you can then finish the wire from the
other end. This can be
a
bit tricky and you should ask for help if things don't seem right to
you.
In general, if you see an "X" at the end of the wire, that means the
wire
isn't connected at that point. And if a wire touches an input or
output, it
is connected to that location. You can test for this by dragging a
component and making sure the wires move with it. You may find
connecting the wires difficult to begin
with, and you should be using "undo" (ctrl-Z) as needed to remove
mistakes.
Try your best to draw your circuit so it looks like this:
Congratulations, you've drawn your first circuit in Quartus! There is a fair bit more to do, but you've finished the design aspect. At this time it is worth noting that there are other ways to do some of the things we've done. For example, components can also be automatically connected by wires if you place them touching one another and then drag them apart. (If this doesn't work, you should check to see that the "rubberbanding" icon is selected. You can also call up the "Symbol tool" by double-clicking openspace in the design pane (though the repeat-insert mode will not be checked by default).
To make sure that all wires are connected and none of the components are used incorrectly you can simply pick-up each device and move it around. Its wires should stay connected (again, assuming the "rubberbanding" icon is selected.)
Again, this would be a good time to save the project. Quartus
seems to
crash every
now and again. So save early and often.
Your lab assignments will require you to submit an image of
your schematic. To create a PDF of your schematic select,
File-->Print, and then Print to File (PDF). You can also select the
directory path in this window.
You might imagine the best way to test our design is to provide
all the input combinations in Table 1. One way to do this is with a
hardware descripton language (HDL) called Verilog. The file and
specification is commonly refered to as a test bench. An example of a
test bench for the majority voter that tests for all the combinations
in table 1 follows.
// means a
comment follows
`timescale 1 ns/1 ns //time scale for the test bench
end
The test bench basically tests your design with a test
procedure. You can think of your majority voter schematic as a module
having 3 input ports A, B and C and one output port M. We could define
a functional reference to the voter as tutorial (A, B, C, M). You might
imagine a test procedure that sets the values of a row of the truth
table to the inputs, waits a bit so you can see the output, and then
sets the next row until all the combinations are tried. This can be
done
with a Verilog initial procedure. It simply sets values to the test
inputs with a delay specified for each case. In this test #10 specifies
a delay of 10ns. Next, we must connect the test variables to the
majority voter logic in the "tutorial" top-level module. Let's look at
the case of port A. The
.A part references the port A defined in your schematic. The A_s part
references your variable in the test bench. Together .A(A_S) completes
the
connection. This notation is order independent. For example, the
connections could have been listed in opposite order: tutorial
t1(.M(M_s), .C(C_s), .B(B_s), .A(A_s)).
Let's create the test bench file. In the Quartus project manager
select File-->new-->Design Files-->Verilog HDL File to
create a new Verilog file. Copy the test bench above and paste into a
Verilog file. Save the file as tutorialtb.v. Notice the icon with a
check mark in the tool bar just above the open file window. Clicking
this will perform a syntax check on your file. It should be ok. Try
removing, say, one of the semicolons in the test procedure, save the
file, and
check again. The error report should give you line specific error
information. Fix the error, check it, and save it.
Quartus uses a common industry simulation tool known as ModelSim
for simulation testing. While ModelSim can be run independently of
Quartus, Quartus and ModelSim have collaborated to provide a version
that can be invoked from Quartus. The advantage is Quartus will pass
all the design, simulation and library files that ModelSim needs, but
some setup is required in Quartus first.
First, you must tell Quartus that you wish to use the
ModelSim-Altera simulation tool. Go to Assignments
→ Settings → EDA Tool
Settings → Simulation, and in
the Tool name window select ModelSim-Altera. In the "Format for output
netlist" window, select Verilog HDL. In the time scale window select 1
ns. The output directory should be simulation/modelsim. Keep this
window
open; there is more to do.
Next, you must provide Quartus with your test bench module name
(tutorialtb) and the location and name of the file. To do this, select
the "Compile test bench:" settings (under NativeLink settings) and
click on the "Test Benches..." button. A window will open, click New.
In the "Test bench name" field, enter "tutorialtb". The "Top level
module in test bench" field will
automatically fill. In the "test bench files" field, browse for your
file tutorialtb.v and add it to the list. Keep all the other settings
as they are. Click OK, saving the windows. Your
settings window should now look like this:
Finally, select the "More EDA Netlist Writer Settings..." button and change the "Generate netlist for functional simulation only" setting to On. This specifies that you are performing a functional simulation. Click OK for both windows.
One last step before we actually run ModelSim. We must check to see if the link to the ModelSim executable is setup. Under tools-->Options you should see the following screen with the path shown in the ModelSim-Altera field. If not, enter the path shown below.
With these settings in place, you must run a compilation to generate all the necessary files. Select Processing → Start Compilation, or click the purple "Start Compilation" button on the toolbar. The compilation should finish successfully. Invistigate any warnings, critical warnings, or errors.
If this completes without errors, you can invoke ModelSim by selecting Tools → Run Simulation Tool → EDA Gate Level Simulation. If there are no errors in your design, ModelSim will open. If you see errors in the ModelSim console window, you will have to go back and fix your design or test bench file (expand the ModelSim console to view all the information about the error). If all goes well, you should see a simulation window with your input and output ports and a simulation waveform. Click on the waveform window and a yellow cursor will appear. Zoom in by clicking on the blue "Zoom Full" magnification button to see the entire simulation. The simulation should look something like this:set_location_assignment PIN_AB28 -to A
set_location_assignment PIN_AC28 -to B
set_location_assignment PIN_AC27 -to C
set_location_assignment PIN_G19 -to M
set_location_assignment PIN_AB28 -to SW[0]
set_location_assignment PIN_AC28 -to SW[1]
set_location_assignment PIN_AC27 -to SW[2]
set_location_assignment PIN_G19 -to LEDR[0]
Compile Design
Now, compile your project again to incorporate your new location assignments. Simply click this button in Quartus tool bar.
You may see a few warnings regarding no clocks found in the design and
a few others as shown below. These can be safely ignored.
Load the Design to Kit
Next, you can download the synthesized circuit to the FPGA via the USB cable that connects the DE2 to the computer that is running Quartus.
First, turn on the DE2 (if it's not already on) by pressing the big red button on the upper left. This should light up the blue power LED (upper left).
No open the programer by clicking on this button in the toolbar.
The following window will open.
Click the Add File button and browse to the output_files directory . You should know see a tutorial.sof file. Select this and the following screen should open.
The tutorial.sof file is the programming file. Select this line and click start. You should see an indicator in the progress window.
If a "no hardware" message is shown in the box in the upper left instead of USB-Blaster. Select the Hardware Setup button, choose USB blaster and save. The kit has to be turned on and the USB cable connected from the kit to the computer for the device to be detected.