KJP BlackJack

Home ||| Hardware Design ||| Software Design ||| Media ||| Member Task Distribution ||| High Level Design ||| Results ||| References ||| Conclusion

Hardware Design

There are several high level functions that support the different components used in hardware. Each one of the functions created had an address decoder written in Verilog that was used in the macros to generate the right TA_BAR signal and other control signals if needed.

Speaker:
In order for us to produce some sounds for our game we needed to generate square wave signals at a particular frequency. We accomplished this by dividing the processors clock by the number needed to generate a specific frequency. To determine what frequency to use, we wrote to a specific address that was mapped to the speaker. For example; the processor had a 10MHz clock and if we needed to create 800 Hz frequency square wave, we divided the clock by (100000/800). To implement the design we used an address decoder, 8 bit counters, 16-bit comparators, flip-flops and some logic gates.

Controller:
For the Nintendo-8 controller, we needed to produce the right timing signal at the right frequency in order for it to work. For example: we needed to produce a latch signal at a frequency of 166.66 Hz with a 10% duty cycle and a pulse signal at 83.33 Hz with a 50% duty cycle. We accomplished this by dividing the processor clock (10MHz). We continuously generated the pulse and latch signals, stored the sent data in an 8 bit shift register, sent that data to another 8-bit flip-flop register after getting the data, and we just read the values from the flip-flop register as we needed. We used an address decoder, 8-bit counters, 8-bit registers, 8-bit shift registers, 16-bit comparators, flip-flops and some logic gates.

Data write/Command write/Data read/Status read:
Data write, Command write, Data read and Status read functions were pretty much created the same way, except the only differences were the addresses used for each function and the control signals that were generated. For example, writes don’t generate a PD_ENABLE signal and the TA_BAR signal comes at different times when comparing reads to writes. Each function used an address decoder, flip-flops, and some logic gates.