Hardware Design
Our hardware design consists of a few different components:
The LCD controller, the touchscreen controller, and the
pulse-width modulator controller.
The basic design of all the hardware interfaces was the
same. The address on the bus is read by the various address
decoders and whichever module is to run generates a
separate TA_BAR signal depending on what it needs to do.
Also, for writes, in each hardware module there are
flip-flops containing relevant data to the operation.
The LCD controller was mapped to address 0x2300000 and
generated one of 5 TA_BAR signals depending on whether you
wanted to read, write, reset it, etc. The reset TA_BAR had
to come after a 900 ns delay, and thus could not simply be
generated only two D-flip flops for wait states. The rest
of the TA_BAR signals were run through two D flip-flops
each to generate the necessary wait states and then each
respectively used as clock enables to D flip-flops with
clock enables, which held relevant data to each operation.
The touchscreen controller also operated on the same
principle as the LCD controller, using address 0x2500000.
The pulse-width modulator controller (0x2600000) also
performed bus transactions in the same way as the LCD and
touchscreen controller, but also had a special PWM
sequential logic module to generate the pulse itself. This
module was simply a finite-state machine programmed in
Verilog which output the pulse and whether or not the servo
should be on depending on a counter, which was programmed
within the FSM to increment on every positive clock edge.
These components interfaced with components we had created
previously and adapted to the expansion board: the ADC
controller and the servo (motor) controller.