A Low Power Low Frequency Sample and Hold Circuit for Implantable Pacemaker

Ali Ahmed, Guan Huang, Fu Sun

Our project is aimed at designing a low power low frequency sample and hold circuit for use in implantable pacemaker. Sample and hold circuit is critical in converting analog signal to digital signal. It samples the analog signal and holds its value until the analog to digital converter can process the information. We plan to implement the design using switched capacitor circuit.

Due to the fact that the device will remain in human body for 5-10 years with one battery, power consumption is of primary concern. We propose to solve the problem by biasing all the transistors in subthreshold region to reduce the power. Another challenge is to minimize the signal drift during the hold mode. We plan to supply a self-adjustable leakage cancellation current to compensate the leakage effect on the hold capacitor.

Our goal is to design a sample and hold circuit with a sampling frequency of 10 Hz, a hold time of 100ms, and power consumption in the range of nano Watts.

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