Sense Amplifier Project

Neal Moyer, Sheeba Saraswathy, Fei Xu

In today's computers, logic latency scales down with decreasing device dimensions, and memory latency becomes more limiting to overall performance. A challenge is presented here in that memory read latency is limited because memory cells are designed with minimum device dimensions, so the data drivers are weak. A voltage sense amplifier can speed up the read operation of memory by sensing small initial changes in the data line and driving the stored value to the output quickly. This project addresses voltage sense amplifier design, with the focus on high yield and low sensing delay. Offset voltage will be a consideration for yield, and capacitance management will be a consideration for speed. A sense amplifier’s position in the memory array can also be leveraged to provide fault detection. The inputs to a sense amp must be opposite data states, and this design will detect if this is not the case.

• Report
• Presentation