Lectures

• Lecture 1 Manufacturing, intro [1.1-1.3 (review), 2.2, WH 3.2]


• Lecture 2 Design rules & layout. 2.3, insert A, WH 1.5, WH 3.3


• Lecture 3 Design flows [8.1-8.4]


• Lecture 4 CMOS review [5.4, 5.5, 6.2, 6.3]


• Lecture 5 Interconnect review [4.3, 9.2, 9.3]


• Lecture 6 Project architecture and LE [Notes]


• Lecture 7 Logical effort [Notes]


• Lecture 8 Logical effort, adders [11.1-11.3.1]


• Lecture 9 Adders [11.3.2-11.3.3]


• Lecture 10 Multipliers [11.4]


• Lecture 11 Shifters [11.5, WH 10.8]


• Lecture 12 Low-power ALUs [11.7]


• Lecture 13 Timing, skew/jitter [10.1-10.3]


• Lecture 14 Continue timing, D-Q, pulsed latches [10.3, 7.4]


• Lecture 15 Design for test [Insert H.3, CBF Ch. 25]


• Lecture 16 Synthesis/APR flow, Verilog overview [Notes, WH 8.4]


• Lecture 17 Memory core and peripherals [12.2, 12.3]


• Lecture 19 Memory reliability and power [12.4, 12.5]


• Lecture 20 System-level power reduction techniques [6.4.2, CBF Ch. 4]


• Lecture 21 Clock distribution [10.3.3, 10.6, CBF Ch. 13]


• Lecture 22 Advanced interconnect[9.5]


• Lecture 23 Power distribution [WH 12.3, CBF Ch. 24]