Schedule

(Printable version)

	Sunday	Monday	Tuesday	Wednesday	Thursday	Friday	Saturday
					1	2	3
Jan 2009	4	5	6	7	8 Lec1 Manufacturing, intro	9	10
	11	12	13 Lec2 Design rules & layout Tutorial1 7-9pm 1620 East CSE	14	15 Lec3 Design flows	16 HW1 due	17
	18	19 CAD1 due	20 Lec4 CMOS review	21	22 Lec5 Interconnect review	23	24
	25	26 CAD2 due	27 Lec6 Project architecture and LE HW2 due	28	29 Lec7 Logical effort	30	31
Feb 2009	1	2	3 Lec8 Logical effort, adders	4	5 Lec9 Adders	6 CAD3 due	7
	8	9	10 Lec10 Multipliers HW3 due	11	12 Lec11 Shifters	13 Tutorial2 4:30-5:30pm during discussion	14
	15	16	17 Lec12 Low-power ALUs CAD4 due	18	19 Quiz1	20	21
	22	23	24 no classes, spring break	25	26 no classes, spring break	27	28
Mar 2009	1	2	3 Lec13 Timing, skew/jitter CAD5 due	4	5 Lec14 Continue timing, D-Q, pulsed latches	6	7
	8	9	10 Lec15 Design for test CAD6 due	11	12 Lec16 Synthesis/APR flow, Verilog overview	13	14
	15	16	17 Lec17 Memory core and peripherals HW4 due	18	19 Lec18 "Active CMOS Biochips for Electrochemical DNA Detection" by Peter Levine, Columbia University	20	21
	22	23	24 Lec19 Memory reliability and power CAD7 due	25	26 System-level power reduction techniques HW5 due	27	28
	29	30	31 Lec20 System-level power reduction techniques	1	2 Lec21 Clock distribution	3	4
Apr 2009	5	6	7 Lec22 Advanced interconnect	8	9 Lec23 Power distribution CAD8 due	10	11
	12	13	14 Lec24 Advanced topics/overflow	15	16 Quiz2	17	18
	19	20	21 Project Presentations HW6 due	22	23	24 Final Project Demos	25
	26	27 HW7 Final report due	28	29	30