EECS 627

VLSI Design II

 

 

Instructor: 

Prof. David Blaauw, blaauw _at_ umich.edu, 763-4526, 4749 CSE

TA:

Ganesh Dasika,  gdasika _at_ eecs.umich.edu

Lectures:

Monday/Wednesday 1:30 - 3:00,  3427 EECS

Lab Recitation: 

Friday 1:30 - 2:30, 3427 EECS 

Web address: 

http://www.eecs.umich.edu/courses/eecs627/w06

News group:

news.eecs.umich.edu/umich.eecs.class.627

Phorum:

The EECS phorum. You will need to create an account to be able to post.

Class email alias:

eecs627@eecs.umich.edu
send email to eecs627-request@eecs.umich.edu with subject "subscribe" to subscribe

Office Hours:

Blaauw:  Wednesday 3-5pm, 4749 CSE

Ganesh:  Monday-Thursday 10-11am, DC3NE

Announcements: 

Course Description: 

This course will address advanced issues in VLSI design, covering the following topics: design methodologies, circuit design using logic effort, advanced static and dynamic logic circuit styles, noise sources and signal integrity in digital design, design techniques for dynamic and static power reduction, adiabatic logic, power supply issues, interconnect analysis and transmission line modeling, clocking and synchronization, and SOI design issues, and process variation. Students are expected to complete a substantial design project as part of the course.

Prerequisites: 

EECS 427 (VLSI Design) or equivalent.


Course Syllabus: syllabus  calendar

Course Materials:

The main course book is:

A. Chandrakasan, W. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2001


In addition, selected sections from the following books will be used:

I. Sutherland, B. Sproull, D. Harris, Logic Effort - designing fast CMOS Circuits Academic Press, 1999

K. Bernstein, N. Rohrer, SOI - Circuit design Concepts, Kluwer Academic Publishers, 2000

K. Bernstein, K. Carrig, C. Durham, P. Hansen, D. Hogenmiller, E. Nowak, N. Rohrer, High Speed CMOS Design Styles, Kluwer Academic Publishers , 1998

D. Harris, Skew-Tolerant Circuit Design, Morgan Kaufmann, 2000

The course is strongly driven from lecture notes and students are not required to buy the course book. The main course book will be on reserve in the library.

Readings are listed in the course syllabus.

Other helpful Books and Pertinent Literature

Assignments:

The course project: The course assignments are centered around substantial design projects completed by student teams. Teams can vary in size based on the size of the project. Preferred team size is 3 - 4 students. Teams can suggest their own ideas for a project or choose from a list of project ideas . Projects must include developing a behavioral model, a verification environment, a synthesizable Verilog description, synthesis, design for test, placement and routing, LVS/DRC and timing back annotation. Projects may include custom modules, analog or mixed signal components, and new design techniques or logic circuit families. The project grade is based on two intermediate design reviews and a final design review.  Each review consists of a written report and an oral presentation by a team member. A different team member is expected to present in each project review. In addition, each team will hand in a project proposal at the start of the semester to identify their project, which is not graded. Please follow the requirements for project proposal and design reviews .  Project reviews are graded both on technical content and presentation quality. It is imperative that students start on their projects at the start of the term and continue to work diligently through the semester.

Lab assignments: In order to give students familiar with the design flow, there are three lab assignments. These assignments will cover simple Verilog, simulation, synthesis, placement and routing, LVS and DRC exercises. Each Lab assignment will be discussed in Recitation and will be graded.

Exams: One midterm exam will be given that middle of the semester and one final exam.  The final exam will not be cumulative and will only cover class material covered after the midterm.

Grading:

Term Project:

55% (design review 1: 10%, design review 2: 10%, final report: 35% )

Exams:

40% (each exam 20%)

Assignment:

5% (each assignment weighted equally)

 

Sources of Help:

Newsgroup
TA
IEEE Xplore (for referring to IEEE journals and conference proceedings
Online materials from previous years