Prof. Thomas F. Wenisch

Over the past several years, a paradigm shift has occurred in the microprocessor design industry. In the past, improvements in silicon manufacturing technology have enabled steady increases in transistor density, processor clock frequency, and processing speed. Industry projections indicate that transistor density will continue increasing for at least another decade. Unfortunately, power and thermal constraints have slowed the march of clock speed. Moreover, design complexity, verification effort, and scalability issues in centralized structures impede further performance improvement in monolithic designs.

Instead of designing increasingly-complex monolithic architectures, processor manufacturers have turned to multi-core architectures, where several processor cores are integrated on a single die. Although the multi-core design paradigm improves scalability and eases complexity and validation challenges, it leaves the programmer, compiler, or run-time system to identify parallel tasks to run on each core. While this challenge exists in traditional multiprocessors, our need to find solutions has become more immediate; our ability to keep cores occupied with useful work will soon become the limiting factor in continued application performance improvement.

Just as technological evolution is now pushing processor architects towards multi-core designs, the "microprocessor revolution" of the 80's and 90's led enterprise IT architects from mainframes to the server- and blade-filled data centers of today. However, as data center density has increased, so, too, have operating costs. Today's data centers consume megawatts of power and their cooling systems consume megawatts more. We must find ways to improve data center power-efficiency and manageability while maintaining performance, reliability, and availability.

My research agenda focuses on the question of how to leverage multi-core designs to continue the trend of exponentially improving performance and cost- performance at the chip, system, and data center level. My immediate research plans focus on three questions:

1. How can we improve the programmability/debuggability of multi-core systems? What kind of support can we provide in hardware to make parallel programming easier? Can we co-design hardware and library/language facilities for writing parallel code? Can we add support to detect programming errors like atomicity violations and data races at run time? How can we encapsulate details of the hardware, such as the memory system architecture or number of cores, so that software performance continues to scale in future chip generations?
2. How can we leverage emerging "disruptive" technologies in multi-core architectures? A variety of disruptive technologies that may radically alter the tradeoffs guiding current computer system designs are likely to mature within the next decade. I am interested in novel architectures that try to exploit such technologies. Two examples that seem particularly promising in the 5-10 year time frame are 3D die stacking (vertical bonding of separately-manufactured silicon dice into a 3D chip), and silicon photonics (intra- and inter-chip optical communications).
3. How can we architect energy- and cost-efficient data centers for the enterprise computing? In many data centers, the physical infrastructure (temperature control, physical security, power distribution) and IT infrastructure (networking and computing systems) are managed by different groups, often leading to massive overprovisioning and inefficiency. How can we redesign the physical layout and logical operation of the data center to reduce energy needs?

A longer summary of my past and future research is available here.