LCD Character Display
Display InitializationNormal Functioning Mode
LCD Enable Signal Generation
LCD Software Drivers
The display presented several unique challenges due to its stringent (and slow) timing requirements. Since the two main input routines to the display were constantly repeated and required very complex timing, it was decided to implement the controls for this in hardware so as to simplify software and eliminate the need for interrupt routines to generate complex timing signals.
Display Initialization
Since the display was initialized through instructions, as opposed to power supply signals, a consistent, flexible interface was desired. The main idea was to allow the core to simply “write” to an address that would decode into an LCD_init command. Again, the 10:1 divided 1Mhz clock was used to generate the appropriate timings for creation of signals.Normal Functioning Mode
Normal functioning mode was mainly controlled by software to allow for the most flexibility. Due to the congruence of the LCD_EN signal, a module was produced to generate the appropriate signal for both normal mode and initialization. During normal mode, the core need only set 10 LSBs in a register to an LCD command (corresponding to RS/WR/DB7-DB0), write that register to a memory location, and all the necessary signals are automatically generated. Unfortunately, it was a problem that the minimum length to wait for instruction execution (without reading the busy flag) was 40us. This presented a problem as the core could easily produce an LCD instruction every 100ns. The ideal solution was to build an LCD instruction buffer module that could accept commands and issue them to the display as it became available. Unfortunately, Xilinx Verilog compilation is restrictive when creating arrays of variables and the initial attempt caused unforeseen errors and chaos. Instead, it was proposed to simply store each instruction in a memory block (similar to lab 4) and maintain a head and tail pointer to the memory. However, this proved overly complex, and since CPU usage was not a concern, the problem was solved with a simple C-function that executed a time waste for loop.LCD Enable Signal Generation
To send any command to the LCD display, a very well-defined enable signal must be generated to initiate the transaction. In addition, there are several requirements on the period between enables and setup/hold times on data. These restrictions were met with an LCD enable generator module. If the proper time between enables was met, the module would output a ready signal, allowing the LCD interface module to send the next instruction to the display and reinitiate the enable generator module. This solution proved very effective and removed considerable code complexity and time expense from the responsibility of the core.