EECS 452: Digital Signal Processing Design Laboratory

Overview

There will be six homework assignments, six lab assignments, and one class project. The approximate due dates for all of this can be found below as well as on the class schedule.

Lab assignments

• General lab policies etc.
• CCS tutorial
• Lab 1: Introduction to the C5510 DSK
• Lab 2: Using the C5510 On-Chip Peripherals
• Lab 3: VHDL, FPGAs and other 4-letter words
• Lab 4: More on FPGA.
• Lab 5: FIR and IIR filters.
• Lab 6: Real time FFT.

Homework

Homework is to be handed in at the start of class.

• HW1 due Fri 9/18.
  • HW1 answers.
• HW3b due Wed 9/30.
• HWs 2-6 in one document. HWs 2 and 3 are due Fri 10/2.
  • HW2 and HW3 answers
• HW4 due Fri 10/9.
  • HW4 answers
• HW5 due Fri 11/6. (note the new due date!)
• HW6 due Fri 11/13. (CANCELLED!)

Homework related files:

• fit.m
• quant.m

Project info

• Previous semesters' project reports
• Project proposal due Wed 10/21.
• Design Expo Thu 12/10.
• Final project presentation Mon 12/14.
• Final report due Tue 12/22.